From a27a03ab3cd45145d3b4d2db7ce8c2959f003e54 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Sun, 23 Aug 2020 19:02:39 +0000 Subject: [PATCH] fastlink: fix crc vs data width --- artiq/gateware/rtio/phy/fastlink.py | 2 +- artiq/gateware/rtio/phy/phaser.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/artiq/gateware/rtio/phy/fastlink.py b/artiq/gateware/rtio/phy/fastlink.py index 3f84bb6a8..891df9b06 100644 --- a/artiq/gateware/rtio/phy/fastlink.py +++ b/artiq/gateware/rtio/phy/fastlink.py @@ -100,7 +100,7 @@ class SerDes(Module): ), If(i == t_frame//2 - 2, # inject crc for the last cycle - Cat(crc_data).eq(self.crc.next), + Cat(crc_data[-n_crc:]).eq(self.crc.next), ), ] diff --git a/artiq/gateware/rtio/phy/phaser.py b/artiq/gateware/rtio/phy/phaser.py index eb5cb26b2..3ca3c535e 100644 --- a/artiq/gateware/rtio/phy/phaser.py +++ b/artiq/gateware/rtio/phy/phaser.py @@ -46,7 +46,7 @@ class Phaser(Module): header.we.eq(~self.config.o.address[-1]), header.addr.eq(self.config.o.address), header.data.eq(self.config.o.data), - header.type.eq(0), # reserved + header.type.eq(1), # reserved ), ]