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ad9910: add init bit explanation
Signed-off-by: Robert Jördens <rj@quartiq.de>
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@ -215,6 +215,9 @@ class AD9910:
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raise ValueError("Urukul AD9910 AUX_DAC mismatch")
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delay(50*us) # slack
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# Configure PLL settings and bring up PLL
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# enable amplitude scale from profiles
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# read effective FTW
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# sync timing validation disable (enabled later)
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self.write32(_AD9910_REG_CFR2, 0x01010020)
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self.cpld.io_update.pulse(1*us)
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cfr3 = (0x0807c100 | (self.pll_vco << 24) |
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