From 9fb850ae75a4f2f29694ec523cd50af15052d7b5 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Robert=20J=C3=B6rdens?= <rj@quartiq.de>
Date: Mon, 5 Nov 2018 12:52:33 +0000
Subject: [PATCH] ad9910: add init bit explanation
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Signed-off-by: Robert Jördens <rj@quartiq.de>
---
 artiq/coredevice/ad9910.py | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/artiq/coredevice/ad9910.py b/artiq/coredevice/ad9910.py
index 6b679d826..3977190a2 100644
--- a/artiq/coredevice/ad9910.py
+++ b/artiq/coredevice/ad9910.py
@@ -215,6 +215,9 @@ class AD9910:
                 raise ValueError("Urukul AD9910 AUX_DAC mismatch")
             delay(50*us)  # slack
         # Configure PLL settings and bring up PLL
+        # enable amplitude scale from profiles
+        # read effective FTW
+        # sync timing validation disable (enabled later)
         self.write32(_AD9910_REG_CFR2, 0x01010020)
         self.cpld.io_update.pulse(1*us)
         cfr3 = (0x0807c100 | (self.pll_vco << 24) |