rtio: increase FIFO sizes

2014-09-17 19:53:29 +08:00 · 2014-09-17 19:53:29 +08:00 · 9b8a91e67e
parent d8b9543e1b
commit 9b8a91e67e
1 changed files with 1 additions and 1 deletions
--- a/soc/artiqlib/rtio/core.py
+++ b/soc/artiqlib/rtio/core.py
@ -138,7 +138,7 @@ class _RTIOBankI(Module):


 class RTIO(Module, AutoCSR):
-    def __init__(self, phy, counter_width=32, ofifo_depth=8, ififo_depth=8):
+    def __init__(self, phy, counter_width=32, ofifo_depth=64, ififo_depth=64):
        fine_ts_width = get_fine_ts_width(phy.rbus)

        # Submodules