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mirror of https://github.com/m-labs/artiq.git synced 2024-12-25 03:08:27 +08:00

rtio: use FWFT FIFO with no buffering. This fixes replace operations.

This commit is contained in:
Sebastien Bourdeauducq 2014-09-17 19:53:06 +08:00
parent 0b1ebb1ba5
commit d8b9543e1b

View File

@ -1,6 +1,6 @@
from migen.fhdl.std import *
from migen.bank.description import *
from migen.genlib.fifo import SyncFIFOBuffered
from migen.genlib.fifo import SyncFIFO
from artiqlib.rtio.rbus import get_fine_ts_width
@ -31,7 +31,7 @@ class _RTIOBankO(Module):
fifos = []
for n, chif in enumerate(rbus):
fifo = SyncFIFOBuffered([
fifo = SyncFIFO([
("timestamp", counter_width+fine_ts_width), ("value", 2)],
2 if chif.mini else fifo_depth)
self.submodules += fifo
@ -89,7 +89,7 @@ class _RTIOBankI(Module):
self.sync += If(~chif.oe & chif.o_stb,
sensitivity.eq(chif.o_value))
fifo = SyncFIFOBuffered([
fifo = SyncFIFO([
("timestamp", counter_width+fine_ts_width), ("value", 1)],
fifo_depth)
self.submodules += fifo