adapt to migen/misoc changes

artiq/gateware/drtio/link_layer.py

@@ -3,7 +3,7 @@ from operator import xor, or_
 
 from migen import *
 from migen.genlib.fsm import *
-from migen.genlib.cdc import MultiReg, NoRetiming
+from migen.genlib.cdc import MultiReg
 
 
 class Scrambler(Module):
@@ -240,10 +240,8 @@ class LinkLayer(Module):
         ready_r = Signal()
         ready_rx = Signal()
         self.sync.rtio += ready_r.eq(self.ready)
-        self.specials += [
+        ready_r.attr.add("no_retiming")
-            NoRetiming(ready_r),
+        self.specials += MultiReg(ready_r, ready_rx, "rtio_rx")
-            MultiReg(ready_r, ready_rx, "rtio_rx")
-        ]
         self.comb += [
             self.rx_aux_frame.eq(rx.aux_frame & ready_rx),
             self.rx_rt_frame.eq(rx.rt_frame & ready_rx),
@@ -259,10 +257,10 @@ class LinkLayer(Module):
 
         rx_remote_rx_ready = Signal()
         rx_link_init = Signal()
+        rx.remote_rx_ready.attr.add("no_retiming")
+        rx.link_init.attr.add("no_retiming")
         self.specials += [
-            NoRetiming(rx.remote_rx_ready),
             MultiReg(rx.remote_rx_ready, rx_remote_rx_ready, "rtio"),
-            NoRetiming(rx.link_init),
             MultiReg(rx.link_init, rx_link_init, "rtio")
         ]
 

artiq/gateware/drtio/rt_controller.py

@@ -1,5 +1,5 @@
 from migen import *
-from migen.genlib.cdc import MultiReg, NoRetiming
+from migen.genlib.cdc import MultiReg
 
 from misoc.interconnect.csr import *
 
@@ -44,10 +44,8 @@ class RTController(Module):
         self.sync += If(self.kcsrs.counter_update.re, 
                         self.kcsrs.counter.status.eq(self.counter.value_sys))
         tsc_correction = Signal(64)
-        self.specials += [
+        self.kcsrs.tsc_correction.storage.attr.add("no_retiming")
-            NoRetiming(self.kcsrs.tsc_correction.storage),
+        self.specials += MultiReg(self.kcsrs.tsc_correction.storage, tsc_correction)
-            MultiReg(self.kcsrs.tsc_correction.storage, tsc_correction)
-        ]
         self.comb += [ 
             rt_packets.tsc_value.eq(
                 self.counter.value_rtio + tsc_correction),

artiq/gateware/drtio/rt_packets.py

@@ -3,7 +3,7 @@ from types import SimpleNamespace
 from migen import *
 from migen.genlib.fsm import *
 from migen.genlib.fifo import AsyncFIFO
-from migen.genlib.cdc import PulseSynchronizer, NoRetiming
+from migen.genlib.cdc import PulseSynchronizer
 
 
 def layout_len(l):
@@ -334,7 +334,7 @@ class _CrossDomainRequest(Module):
         ]
         if req_data is not None:
             req_data_r = Signal.like(req_data)
-            self.specials += NoRetiming(req_data_r)
+            req_data_r.attr.add("no_retiming")
             self.sync += If(req_stb, req_data_r.eq(req_data))
         dsync += [
             If(request.o, srv_stb.eq(1)),
@@ -350,7 +350,7 @@ class _CrossDomainNotification(Module):
                  emi_stb, emi_data,
                  rec_stb, rec_ack, rec_data):
         emi_data_r = Signal.like(emi_data)
-        self.specials += NoRetiming(emi_data_r)
+        emi_data_r.attr.add("no_retiming")
         dsync = getattr(self.sync, domain)
         dsync += If(emi_stb, emi_data_r.eq(emi_data))
 

artiq/gateware/rtio/cdc.py

@@ -18,10 +18,8 @@ class GrayCodeTransfer(Module):
         self.sync.rtio += value_gray_rtio.eq(self.i ^ self.i[1:])
         # transfer to system clock domain
         value_gray_sys = Signal(width)
-        self.specials += [
+        value_gray_rtio.attr.add("no_retiming")
-            NoRetiming(value_gray_rtio),
+        self.specials += MultiReg(value_gray_rtio, value_gray_sys)
-            MultiReg(value_gray_rtio, value_gray_sys)
-        ]
         # convert back to binary
         value_sys = Signal(width)
         self.comb += value_sys[-1].eq(value_gray_sys[-1])

artiq/gateware/targets/kc705.py

@@ -8,7 +8,6 @@ from migen.genlib.cdc import MultiReg
 from migen.build.generic_platform import *
 from migen.build.xilinx.vivado import XilinxVivadoToolchain
 from migen.build.xilinx.ise import XilinxISEToolchain
-from migen.fhdl.specials import Keep
 
 from misoc.interconnect.csr import *
 from misoc.interconnect import wishbone
@@ -147,22 +146,11 @@ class _NIST_Ions(MiniSoC, AMPSoC):
         self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
         self.csr_devices.append("rtio_moninj")
 
-        self.specials += [
+        self.rtio_crg.cd_rtio.clk.attr.add("keep")
-            Keep(self.rtio.cd_rsys.clk),
-            Keep(self.rtio_crg.cd_rtio.clk),
-            Keep(self.ethphy.crg.cd_eth_rx.clk),
-            Keep(self.ethphy.crg.cd_eth_tx.clk),
-        ]
-
-        self.platform.add_period_constraint(self.rtio.cd_rsys.clk, 8.)
         self.platform.add_period_constraint(self.rtio_crg.cd_rtio.clk, 8.)
-        self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 8.)
-        self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 8.)
         self.platform.add_false_path_constraints(
-            self.rtio.cd_rsys.clk,
+            self.crg.cd_sys.clk,
-            self.rtio_crg.cd_rtio.clk,
+            self.rtio_crg.cd_rtio.clk)
-            self.ethphy.crg.cd_eth_rx.clk,
-            self.ethphy.crg.cd_eth_tx.clk)
 
         self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio,
             self.get_native_sdram_if())

artiq/gateware/targets/kc705_drtio_master.py

@@ -3,7 +3,6 @@
 import argparse
 
 from migen import *
-from migen.fhdl.specials import Keep
 
 from misoc.targets.kc705 import MiniSoC, soc_kc705_args, soc_kc705_argdict
 from misoc.integration.builder import builder_args, builder_argdict
@@ -44,17 +43,6 @@ class Master(MiniSoC, AMPSoC):
         self.submodules.drtio = DRTIOMaster(self.transceiver)
         self.register_kernel_cpu_csrdevice("drtio")
 
-        self.specials += [
-            Keep(self.ethphy.crg.cd_eth_rx.clk),
-            Keep(self.ethphy.crg.cd_eth_tx.clk),
-        ]
-
-        platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 8.)
-        platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 8.)
-        platform.add_false_path_constraints(
-            self.ethphy.crg.cd_eth_rx.clk,
-            self.ethphy.crg.cd_eth_tx.clk)
-
 
 def main():
     parser = argparse.ArgumentParser(