mirror of https://github.com/m-labs/artiq.git
add has_dds, use config flags
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@ -137,6 +137,8 @@ class _NIST_Ions(MiniSoC, AMPSoC):
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self.register_kernel_cpu_csrdevice("i2c")
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self.register_kernel_cpu_csrdevice("i2c")
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self.config["I2C_BUS_COUNT"] = 1
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self.config["I2C_BUS_COUNT"] = 1
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self.config["HAS_DDS"] = None
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def add_rtio(self, rtio_channels):
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def add_rtio(self, rtio_channels):
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self.submodules.rtio_crg = _RTIOCRG(self.platform, self.crg.cd_sys.clk)
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self.submodules.rtio_crg = _RTIOCRG(self.platform, self.crg.cd_sys.clk)
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self.csr_devices.append("rtio_crg")
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self.csr_devices.append("rtio_crg")
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@ -198,7 +200,7 @@ class NIST_QC1(_NIST_Ions):
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self.config["RTIO_FIRST_DDS_CHANNEL"] = len(rtio_channels)
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self.config["RTIO_FIRST_DDS_CHANNEL"] = len(rtio_channels)
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self.config["RTIO_DDS_COUNT"] = 1
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self.config["RTIO_DDS_COUNT"] = 1
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self.config["DDS_CHANNELS_PER_BUS"] = 8
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self.config["DDS_CHANNELS_PER_BUS"] = 8
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self.config["DDS_AD9858"] = True
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self.config["DDS_AD9858"] = None
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phy = dds.AD9858(platform.request("dds"), 8)
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phy = dds.AD9858(platform.request("dds"), 8)
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self.submodules += phy
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy,
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rtio_channels.append(rtio.Channel.from_phy(phy,
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@ -272,8 +274,8 @@ class NIST_CLOCK(_NIST_Ions):
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self.config["RTIO_FIRST_DDS_CHANNEL"] = len(rtio_channels)
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self.config["RTIO_FIRST_DDS_CHANNEL"] = len(rtio_channels)
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self.config["RTIO_DDS_COUNT"] = 1
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self.config["RTIO_DDS_COUNT"] = 1
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self.config["DDS_CHANNELS_PER_BUS"] = 11
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self.config["DDS_CHANNELS_PER_BUS"] = 11
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self.config["DDS_AD9914"] = True
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self.config["DDS_AD9914"] = None
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self.config["DDS_ONEHOT_SEL"] = True
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self.config["DDS_ONEHOT_SEL"] = None
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phy = dds.AD9914(platform.request("dds"), 11, onehot=True)
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phy = dds.AD9914(platform.request("dds"), 11, onehot=True)
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self.submodules += phy
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy,
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rtio_channels.append(rtio.Channel.from_phy(phy,
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@ -350,8 +352,8 @@ class NIST_QC2(_NIST_Ions):
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self.config["RTIO_FIRST_DDS_CHANNEL"] = len(rtio_channels)
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self.config["RTIO_FIRST_DDS_CHANNEL"] = len(rtio_channels)
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self.config["RTIO_DDS_COUNT"] = 2
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self.config["RTIO_DDS_COUNT"] = 2
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self.config["DDS_CHANNELS_PER_BUS"] = 12
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self.config["DDS_CHANNELS_PER_BUS"] = 12
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self.config["DDS_AD9914"] = True
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self.config["DDS_AD9914"] = None
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self.config["DDS_ONEHOT_SEL"] = True
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self.config["DDS_ONEHOT_SEL"] = None
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for backplane_offset in range(2):
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for backplane_offset in range(2):
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phy = dds.AD9914(
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phy = dds.AD9914(
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platform.request("dds", backplane_offset), 12, onehot=True)
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platform.request("dds", backplane_offset), 12, onehot=True)
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@ -206,10 +206,11 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
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rtio_channels.append(rtio.Channel.from_phy(
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rtio_channels.append(rtio.Channel.from_phy(
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phy, ofifo_depth=64, ififo_depth=64))
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phy, ofifo_depth=64, ififo_depth=64))
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self.config["HAS_DDS"] = None
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self.config["RTIO_FIRST_DDS_CHANNEL"] = len(rtio_channels)
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self.config["RTIO_FIRST_DDS_CHANNEL"] = len(rtio_channels)
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self.config["RTIO_DDS_COUNT"] = 1
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self.config["RTIO_DDS_COUNT"] = 1
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self.config["DDS_CHANNELS_PER_BUS"] = 8
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self.config["DDS_CHANNELS_PER_BUS"] = 8
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self.config["DDS_AD9858"] = True
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self.config["DDS_AD9858"] = None
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dds_pins = platform.request("dds")
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dds_pins = platform.request("dds")
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self.comb += dds_pins.p.eq(0)
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self.comb += dds_pins.p.eq(0)
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phy = dds.AD9858(dds_pins, 8)
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phy = dds.AD9858(dds_pins, 8)
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@ -105,15 +105,15 @@ static mut API: &'static [(&'static str, *const ())] = &[
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api!(rtio_input_timestamp),
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api!(rtio_input_timestamp),
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api!(rtio_input_data),
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api!(rtio_input_data),
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#[cfg(has_rtio_dds_count)]
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#[cfg(has_dds)]
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api!(dds_init),
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api!(dds_init),
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#[cfg(has_rtio_dds_count)]
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#[cfg(has_dds)]
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api!(dds_init_sync),
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api!(dds_init_sync),
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#[cfg(has_rtio_dds_count)]
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#[cfg(has_dds)]
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api!(dds_batch_enter),
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api!(dds_batch_enter),
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#[cfg(has_rtio_dds_count)]
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#[cfg(has_dds)]
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api!(dds_batch_exit),
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api!(dds_batch_exit),
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#[cfg(has_rtio_dds_count)]
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#[cfg(has_dds)]
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api!(dds_set),
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api!(dds_set),
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api!(i2c_init),
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api!(i2c_init),
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