From 99ad9b591796414f1fe550ccf928a2626a92536d Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 8 Nov 2016 23:33:03 +0800 Subject: [PATCH] add has_dds, use config flags --- artiq/gateware/targets/kc705.py | 12 +++++++----- artiq/gateware/targets/pipistrello.py | 3 ++- artiq/runtime.rs/libksupport/api.rs | 10 +++++----- 3 files changed, 14 insertions(+), 11 deletions(-) diff --git a/artiq/gateware/targets/kc705.py b/artiq/gateware/targets/kc705.py index ea38273d4..486f047f0 100755 --- a/artiq/gateware/targets/kc705.py +++ b/artiq/gateware/targets/kc705.py @@ -137,6 +137,8 @@ class _NIST_Ions(MiniSoC, AMPSoC): self.register_kernel_cpu_csrdevice("i2c") self.config["I2C_BUS_COUNT"] = 1 + self.config["HAS_DDS"] = None + def add_rtio(self, rtio_channels): self.submodules.rtio_crg = _RTIOCRG(self.platform, self.crg.cd_sys.clk) self.csr_devices.append("rtio_crg") @@ -198,7 +200,7 @@ class NIST_QC1(_NIST_Ions): self.config["RTIO_FIRST_DDS_CHANNEL"] = len(rtio_channels) self.config["RTIO_DDS_COUNT"] = 1 self.config["DDS_CHANNELS_PER_BUS"] = 8 - self.config["DDS_AD9858"] = True + self.config["DDS_AD9858"] = None phy = dds.AD9858(platform.request("dds"), 8) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, @@ -272,8 +274,8 @@ class NIST_CLOCK(_NIST_Ions): self.config["RTIO_FIRST_DDS_CHANNEL"] = len(rtio_channels) self.config["RTIO_DDS_COUNT"] = 1 self.config["DDS_CHANNELS_PER_BUS"] = 11 - self.config["DDS_AD9914"] = True - self.config["DDS_ONEHOT_SEL"] = True + self.config["DDS_AD9914"] = None + self.config["DDS_ONEHOT_SEL"] = None phy = dds.AD9914(platform.request("dds"), 11, onehot=True) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, @@ -350,8 +352,8 @@ class NIST_QC2(_NIST_Ions): self.config["RTIO_FIRST_DDS_CHANNEL"] = len(rtio_channels) self.config["RTIO_DDS_COUNT"] = 2 self.config["DDS_CHANNELS_PER_BUS"] = 12 - self.config["DDS_AD9914"] = True - self.config["DDS_ONEHOT_SEL"] = True + self.config["DDS_AD9914"] = None + self.config["DDS_ONEHOT_SEL"] = None for backplane_offset in range(2): phy = dds.AD9914( platform.request("dds", backplane_offset), 12, onehot=True) diff --git a/artiq/gateware/targets/pipistrello.py b/artiq/gateware/targets/pipistrello.py index f9afa683b..a0a5f0134 100755 --- a/artiq/gateware/targets/pipistrello.py +++ b/artiq/gateware/targets/pipistrello.py @@ -206,10 +206,11 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd rtio_channels.append(rtio.Channel.from_phy( phy, ofifo_depth=64, ififo_depth=64)) + self.config["HAS_DDS"] = None self.config["RTIO_FIRST_DDS_CHANNEL"] = len(rtio_channels) self.config["RTIO_DDS_COUNT"] = 1 self.config["DDS_CHANNELS_PER_BUS"] = 8 - self.config["DDS_AD9858"] = True + self.config["DDS_AD9858"] = None dds_pins = platform.request("dds") self.comb += dds_pins.p.eq(0) phy = dds.AD9858(dds_pins, 8) diff --git a/artiq/runtime.rs/libksupport/api.rs b/artiq/runtime.rs/libksupport/api.rs index b9788be26..f30b099b0 100644 --- a/artiq/runtime.rs/libksupport/api.rs +++ b/artiq/runtime.rs/libksupport/api.rs @@ -105,15 +105,15 @@ static mut API: &'static [(&'static str, *const ())] = &[ api!(rtio_input_timestamp), api!(rtio_input_data), - #[cfg(has_rtio_dds_count)] + #[cfg(has_dds)] api!(dds_init), - #[cfg(has_rtio_dds_count)] + #[cfg(has_dds)] api!(dds_init_sync), - #[cfg(has_rtio_dds_count)] + #[cfg(has_dds)] api!(dds_batch_enter), - #[cfg(has_rtio_dds_count)] + #[cfg(has_dds)] api!(dds_batch_exit), - #[cfg(has_rtio_dds_count)] + #[cfg(has_dds)] api!(dds_set), api!(i2c_init),