mirror of https://github.com/m-labs/artiq.git
transceiver: init eem media
This commit is contained in:
parent
7ad32d903a
commit
98dff30e88
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from migen import *
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from migen.genlib.cdc import MultiReg
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from migen.genlib.io import DifferentialInput, DifferentialOutput
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from migen.genlib.fifo import AsyncFIFO
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from misoc.cores import gpio
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from misoc.interconnect.csr import *
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from misoc.cores.code_8b10b import SingleEncoder, Decoder
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from artiq.gateware.drtio.core import TransceiverInterface, ChannelInterface
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class RXPhy(Module):
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def __init__(self, i_pads):
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self.o = [Signal() for _ in range(4)]
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for i in range(4):
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self.specials += Instance("IBUFDS",
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i_I=i_pads[i].p,
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i_IB=i_pads[i].n,
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o_O=self.o[i],
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)
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class TXPhy(Module):
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def __init__(self, o_pads):
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self.i = [Signal() for _ in range(4)]
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self.t = [Signal() for _ in range(4)]
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for i in range(4):
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self.specials += Instance("OBUFTDS",
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i_I=self.i[i],
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o_O=o_pads[i].p,
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o_OB=o_pads[i].n,
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# Always chain the 3-states input to serializer
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# Vivado will complain otherwise
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i_T=self.t[i],
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)
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class RXSerdes(Module):
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def __init__(self):
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self.rxdata = [ Signal(10) for _ in range(4) ]
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self.ser_in_no_dly = [ Signal() for _ in range(4) ]
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self.ld = [ Signal() for _ in range(4) ]
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self.cnt_in = [ Signal(5) for _ in range(4) ]
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self.cnt_out = [ Signal(5) for _ in range(4) ]
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self.bitslip = [ Signal() for _ in range(4) ]
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ser_in = [ Signal() for _ in range(4) ]
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shifts = [ Signal(2) for _ in range(4) ]
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for i in range(4):
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self.specials += [
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# Master deserializer
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Instance("ISERDESE2",
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p_DATA_RATE="DDR",
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p_DATA_WIDTH=10,
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p_INTERFACE_TYPE="NETWORKING",
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p_NUM_CE=1,
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p_SERDES_MODE="MASTER",
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p_IOBDELAY="IFD",
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o_Q1=self.rxdata[i][9],
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o_Q2=self.rxdata[i][8],
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o_Q3=self.rxdata[i][7],
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o_Q4=self.rxdata[i][6],
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o_Q5=self.rxdata[i][5],
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o_Q6=self.rxdata[i][4],
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o_Q7=self.rxdata[i][3],
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o_Q8=self.rxdata[i][2],
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o_SHIFTOUT1=shifts[i][0],
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o_SHIFTOUT2=shifts[i][1],
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i_DDLY=ser_in[i],
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i_BITSLIP=self.bitslip[i],
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i_CLK=ClockSignal("eem_sys5x"),
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i_CLKB=~ClockSignal("eem_sys5x"),
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i_CE1=1,
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i_RST=ResetSignal("eem_sys"),
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i_CLKDIV=ClockSignal("eem_sys")),
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# Slave deserializer
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Instance("ISERDESE2",
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p_DATA_RATE="DDR",
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p_DATA_WIDTH=10,
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p_INTERFACE_TYPE="NETWORKING",
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p_NUM_CE=1,
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p_SERDES_MODE="SLAVE",
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p_IOBDELAY="IFD",
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o_Q3=self.rxdata[i][1],
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o_Q4=self.rxdata[i][0],
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i_BITSLIP=self.bitslip[i],
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i_CLK=ClockSignal("eem_sys5x"),
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i_CLKB=~ClockSignal("eem_sys5x"),
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i_CE1=1,
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i_RST=ResetSignal("eem_sys"),
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i_CLKDIV=ClockSignal("eem_sys"),
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i_SHIFTIN1=shifts[i][0],
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i_SHIFTIN2=shifts[i][1]),
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# Tunable delay
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Instance("IDELAYE2",
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p_DELAY_SRC="IDATAIN",
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p_SIGNAL_PATTERN="DATA",
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p_CINVCTRL_SEL="FALSE",
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p_HIGH_PERFORMANCE_MODE="TRUE",
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# REFCLK refers to the clock source of IDELAYCTRL
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p_REFCLK_FREQUENCY=200.0,
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p_PIPE_SEL="FALSE",
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p_IDELAY_TYPE="VAR_LOAD",
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p_IDELAY_VALUE=0,
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i_C=ClockSignal(),
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i_LD=self.ld[i],
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i_CE=0,
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i_LDPIPEEN=0,
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i_INC=1, # Always increment
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# Set the optimal delay tap via the aligner
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i_CNTVALUEIN=self.cnt_in[i],
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# Allow the aligner to check the tap value
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o_CNTVALUEOUT=self.cnt_out[i],
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i_IDATAIN=self.ser_in_no_dly[i],
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o_DATAOUT=ser_in[i]
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),
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# IDELAYCTRL is with the clocking
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]
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class TXSerdes(Module):
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def __init__(self):
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self.txdata = [ Signal(5) for _ in range(4) ]
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self.ser_out = [ Signal() for _ in range(4) ]
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self.t_out = [ Signal() for _ in range(4) ]
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# TX SERDES
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for i in range(4):
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self.specials += Instance("OSERDESE2",
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p_DATA_RATE_OQ="SDR", p_DATA_RATE_TQ="BUF",
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p_DATA_WIDTH=5, p_TRISTATE_WIDTH=1,
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p_INIT_OQ=0b00000,
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o_OQ=self.ser_out[i],
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o_TQ=self.t_out[i],
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i_RST=ResetSignal("eem_sys"),
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i_CLK=ClockSignal("eem_sys5x"),
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i_CLKDIV=ClockSignal("eem_sys"),
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i_D1=self.txdata[i][0],
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i_D2=self.txdata[i][1],
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i_D3=self.txdata[i][2],
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i_D4=self.txdata[i][3],
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i_D5=self.txdata[i][4],
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i_TCE=1, i_OCE=1,
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i_T1=0)
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class MultiEncoder(Module):
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def __init__(self):
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WORDS = 2
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# Keep the link layer interface identical to standard encoders
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self.d = [Signal(8) for _ in range(WORDS)]
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self.k = [Signal() for _ in range(WORDS)]
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# Alignment control: Keep sending K.28.5
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self.align = Signal()
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# Output interface is simplified because we have custom physical layer
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self.output = [Signal(10) for _ in range(WORDS)]
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# Phase of the encoder
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# Alternate crossbar between encoder and SERDES every cycle
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self.phase = Signal()
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# Intermediate registers for output and disparity
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# More significant bits are buffered due to channel geometry
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# Disparity bit is delayed. The same encoder is shared by 2 SERDES
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output_bufs = [Signal(5) for _ in range(WORDS)]
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disp_bufs = [Signal() for _ in range(WORDS)]
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encoders = [SingleEncoder() for _ in range(WORDS)]
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self.submodules += encoders
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for d, k, output, output_buf, disp_buf, encoder in \
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zip(self.d, self.k, self.output, output_bufs, disp_bufs, encoders):
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self.comb += [
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If(self.align,
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encoder.d.eq(0xBC),
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encoder.k.eq(1),
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).Else(
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encoder.d.eq(d),
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encoder.k.eq(k),
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),
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# Implementing switching crossbar
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If(self.phase,
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output.eq(Cat(encoder.output[0:5], output_buf))
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).Else(
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output.eq(Cat(output_buf, encoder.output[0:5]))
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),
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]
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# Handle intermediate registers
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self.sync.eem_sys += [
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disp_buf.eq(encoder.disp_out),
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encoder.disp_in.eq(disp_buf),
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output_buf.eq(encoder.output[5:10]),
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]
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# Unlike the usual 8b10b decoder, it needs to know which SERDES to decode
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class CrossbarDecoder(Module):
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def __init__(self):
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self.raw_input = [ Signal(5) for _ in range(2) ]
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self.d = Signal(8)
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self.k = Signal()
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# Notifier signal when group alignmnet is completed
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self.delay = Signal(2)
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self.phase = Signal()
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# Optional extra stage for both lanes
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self.delay_buf = [ Signal(5) for _ in range(2) ]
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self.sync.eem_sys += [
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self.delay_buf[idx].eq(self.raw_input[idx]) for idx in range(2)
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]
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# Intermediate register for input
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buffer = Signal(5)
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self.submodules.decoder = Decoder()
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# Update phase & synchronous elements
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self.sync.eem_sys += [
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If(~self.phase,
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If(~self.delay[0],
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buffer.eq(self.raw_input[0]),
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).Else(
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buffer.eq(self.delay_buf[0]),
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)
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).Else(
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If(~self.delay[1],
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buffer.eq(self.raw_input[1]),
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).Else(
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buffer.eq(self.delay_buf[1]),
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)
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)
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]
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# Send appropriate input to decoder
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self.comb += [
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If(self.phase,
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If(~self.delay[0],
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self.decoder.input.eq(Cat(buffer, self.raw_input[0])),
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).Else(
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self.decoder.input.eq(Cat(buffer, self.delay_buf[0])),
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)
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).Else(
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If(~self.delay[1],
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self.decoder.input.eq(Cat(buffer, self.raw_input[1])),
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).Else(
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self.decoder.input.eq(Cat(buffer, self.delay_buf[1])),
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)
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),
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]
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self.comb += [
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self.d.eq(self.decoder.d),
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self.k.eq(self.decoder.k),
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]
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class SerdesSingle(Module, AutoCSR):
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def __init__(self, i_pads, o_pads, debug=False):
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# Modules for the IOB
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self.submodules.rx_phy = RXPhy(i_pads)
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self.submodules.tx_phy = TXPhy(o_pads)
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# Serdes Module
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self.submodules.rx_serdes = RXSerdes()
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self.submodules.tx_serdes = TXSerdes()
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# CSR for delay & bitslip
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self.bitslip_sel = CSRStorage(4)
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self.bitslip = CSR()
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for i in range(4):
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self.specials += MultiReg(
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self.bitslip_sel.storage[i] & self.bitslip.re,
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self.rx_serdes.bitslip[i], "eem_sys")
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self.dly_cnt_in_sel = CSRStorage(4)
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self.dly_cnt_in = CSRStorage(5)
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self.dly_ld = CSR()
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for i in range(4):
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self.comb += [
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self.rx_serdes.cnt_in[i].eq(self.dly_cnt_in.storage),
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self.rx_serdes.ld[i].eq(self.dly_cnt_in_sel.storage[i] & self.dly_ld.re),
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]
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self.dly_cnt_out_sel = CSRStorage(4)
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self.dly_cnt_out = CSRStatus(5)
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self.comb += Case(self.dly_cnt_out_sel.storage, {
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(1 << idx): self.dly_cnt_out.status.eq(self.rx_serdes.cnt_out[idx]) for idx in range(4)
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})
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# CSR for global decoding phase
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# This is to determine if this cycle should decode SERDES 0 or 1
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self.decoder_dly = CSRStorage(4)
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dec_dly_cdc = Signal(4)
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self.specials += MultiReg(self.decoder_dly.storage, dec_dly_cdc, "eem_sys")
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# Encoder/Decodfer interfaces
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self.submodules.encoder = MultiEncoder()
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self.submodules.decoders = decoders = Array(CrossbarDecoder() for _ in range(2))
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# Wire up the IOB to serdes modules
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for i in range(4):
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self.comb += [
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self.tx_phy.i[i].eq(self.tx_serdes.ser_out[i]),
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self.tx_phy.t[i].eq(self.tx_serdes.t_out[i]),
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self.rx_serdes.ser_in_no_dly[i].eq(self.rx_phy.o[i]),
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]
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# Control decoders phase
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self.comb += [
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decoders[0].delay.eq(dec_dly_cdc[:2]),
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decoders[1].delay.eq(dec_dly_cdc[2:]),
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]
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# Route encoded symbols to TXSerdes
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self.comb += [
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self.tx_serdes.txdata[0].eq(self.encoder.output[0][:5]),
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self.tx_serdes.txdata[1].eq(self.encoder.output[0][5:]),
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self.tx_serdes.txdata[2].eq(self.encoder.output[1][:5]),
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self.tx_serdes.txdata[3].eq(self.encoder.output[1][5:]),
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]
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# Truncate RX, controllable via CSR
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self.select_odd = CSRStorage(4)
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select_odd_cdc = Signal(4)
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self.specials += MultiReg(self.select_odd.storage, select_odd_cdc, "eem_sys")
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decimated_rxdata = [ Signal(5) for _ in range(4) ]
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for i in range(4):
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self.comb += decimated_rxdata[i].eq(Mux(select_odd_cdc[i],
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self.rx_serdes.rxdata[i][1::2], self.rx_serdes.rxdata[i][0::2]))
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# Route RXSerdes to decoder
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self.comb += [
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decoders[i//2].raw_input[i%2].eq(decimated_rxdata[i]) for i in range(4)
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]
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# Always send out K.28.5 if not aligned
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self.send_align = CSRStorage(reset=1)
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self.specials += MultiReg(self.send_align.storage, self.encoder.align, "eem_sys")
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# Alternate phase
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phase = Signal()
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# Assign to encoder and decoder
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self.comb += [
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self.encoder.phase.eq(phase),
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self.decoders[0].phase.eq(phase),
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self.decoders[1].phase.eq(phase),
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]
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# Phase increment & reset mechanism
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# Reset to 0 when externally triggered
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self.phase_rst = Signal()
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self.sync.eem_sys += If(self.phase_rst,
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phase.eq(0),
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).Else(
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phase.eq(~phase)
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)
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self.phase_out = Signal()
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self.comb += self.phase_out.eq(phase)
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# Interleave data/ctrl update
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self.read_word = CSRStorage(2)
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self.aligned = CSRStatus()
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rx_d = Signal(8)
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rx_k = Signal()
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rx_d_prev = Signal(8)
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rx_k_prev = Signal()
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read_word_cdc = Signal(2)
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self.specials += MultiReg(self.read_word.storage, read_word_cdc)
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self.sync.eem_sys += [
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If(~phase ^ read_word_cdc[0],
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rx_d.eq(decoders[read_word_cdc[1]].d),
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rx_k.eq(decoders[read_word_cdc[1]].k),
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rx_d_prev.eq(rx_d),
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rx_k_prev.eq(rx_k),
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)
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]
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found_align_symbol = Signal()
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self.comb += found_align_symbol.eq(
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(rx_d == 0xBC) & (rx_d_prev == 0xBC)
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& (rx_k == 1) & (rx_k_prev == 1))
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self.specials += MultiReg(found_align_symbol, self.aligned.status)
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layout = [
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("sat_clk_rdy", 2, "satellite"),
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("phase_rdy", 3, "master"),
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("sat_rst", 4, "master"),
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("mst_clk_rdy", 5, "master"),
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("align_mst", 6, "satellite"),
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("align_sat", 7, "master"),
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]
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class EEMSerdes(Module, TransceiverInterface):
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def __init__(self, platform, eem, eem_aux, role="master", start_idx=0):
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self.rx_ready = CSRStorage()
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# Request resources
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# TODO: Expand to support multiple EFCs
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i_pads = [
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platform.request("eem{}_fmc_data_in".format(eem), i) for i in range(4)
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]
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o_pads = [
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platform.request("eem{}_fmc_data_out".format(eem), i) for i in range(4)
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]
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self.submodules.serdes = SerdesSingle(i_pads, o_pads)
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self.submodules.aux = EEMAux(platform, eem_aux, role=role)
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# TODO: Move global phase here
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if role == "master":
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self.comb += self.aux.phase_in.eq(self.serdes.phase_out)
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elif role == "satellite":
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self.comb += self.serdes.phase_rst.eq(self.aux.phase_rst)
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chan_if = ChannelInterface(self.serdes.encoder, self.serdes.decoders)
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self.comb += chan_if.rx_ready.eq(self.rx_ready.storage)
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channel_interfaces = [chan_if]
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TransceiverInterface.__init__(self, channel_interfaces, start_idx=start_idx)
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self.comb += [
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||||
getattr(self, "cd_rtio_rx" + str(start_idx)).clk.eq(ClockSignal("eem_sys")),
|
||||
getattr(self, "cd_rtio_rx" + str(start_idx)).rst.eq(ResetSignal("eem_sys"))
|
||||
]
|
||||
|
||||
|
||||
class EEMAux(Module, AutoCSR):
|
||||
def __init__(self, platform, eem_aux, role="master"):
|
||||
for name, _, src in layout:
|
||||
if name != "sat_rst":
|
||||
tmp = Signal()
|
||||
pad = platform.request(("eem{}_fmc_"+name).format(eem_aux))
|
||||
if src == role:
|
||||
self.specials += DifferentialOutput(tmp, pad.p, pad.n)
|
||||
setattr(self.submodules, name, gpio.GPIOOut(tmp))
|
||||
else:
|
||||
self.specials += DifferentialInput(pad.p, pad.n, tmp)
|
||||
setattr(self.submodules, name, gpio.GPIOIn(tmp))
|
||||
|
||||
sat_rst_pad = platform.request("eem{}_fmc_sat_rst".format(eem_aux))
|
||||
sat_rst_tmp = Signal()
|
||||
if role == "master":
|
||||
self.phase_in = Signal()
|
||||
self.sat_phase_rst = CSR()
|
||||
sat_phase_rst_r = Signal()
|
||||
sat_phase_rst_rr = Signal()
|
||||
sat_phase_rst_cdc = Signal()
|
||||
|
||||
self.specials += MultiReg(self.sat_phase_rst.re, sat_phase_rst_r, "eem_sys")
|
||||
self.sync.eem_sys += sat_phase_rst_rr.eq(sat_phase_rst_r)
|
||||
self.comb += sat_phase_rst_cdc.eq(sat_phase_rst_rr | sat_phase_rst_r)
|
||||
gated_pulse = Signal()
|
||||
self.sync.eem_sys += gated_pulse.eq(sat_phase_rst_cdc & self.phase_in)
|
||||
self.specials += DifferentialOutput(gated_pulse, sat_rst_pad.p, sat_rst_pad.n)
|
||||
|
||||
elif role == "satellite":
|
||||
self.phase_rst = Signal()
|
||||
phase_in_raw = Signal()
|
||||
self.specials += DifferentialInput(sat_rst_pad.p, sat_rst_pad.n, phase_in_raw)
|
||||
self.specials += MultiReg(phase_in_raw, self.phase_rst, "eem_sys")
|
||||
else:
|
||||
ValueError("Invalid role type")
|
||||
Loading…
Reference in New Issue