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kasli: construct DRTIO-EEM modules before adding RTIO

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occheung 2023-09-03 20:29:42 -07:00 committed by Sébastien Bourdeauducq
parent 73ac414912
commit 98904ef4c3
1 changed files with 3 additions and 1 deletions
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4
artiq/gateware/targets/kasli_generic.py
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@ -99,10 +99,12 @@ class GenericMaster(MasterBase):
self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
self.rtio_channels.append(rtio.LogChannel())
self.add_rtio(self.rtio_channels, sed_lanes=description["sed_lanes"])
if has_drtio_over_eem:
self.add_eem_drtio(self.eem_drtio_channels)
self.add_drtio_cpuif_groups()
self.add_rtio(self.rtio_channels, sed_lanes=description["sed_lanes"])
if has_grabber:
self.config["HAS_GRABBER"] = None
self.add_csr_group("grabber", self.grabber_csr_group)