From 97a54046e85f0c377eef6c17cd23ab00e2c577a0 Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Sat, 19 Nov 2016 14:16:06 +0100 Subject: [PATCH] rtio: auto clear output event data and address This is to support channels where variable length event data is well-defined through zero-padding. E.g. in the case of `Spline` zero-padding of events naturally corresponds to low-order knots. Use timestamp change as trigger. This assumes that writes to the timestamp register always precede address and data writes. It does not break support for ganged writes of the same event timestamp and data/address to multiple channels or channel-addresses. --- artiq/gateware/rtio/core.py | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/artiq/gateware/rtio/core.py b/artiq/gateware/rtio/core.py index a248632da..4d5624684 100644 --- a/artiq/gateware/rtio/core.py +++ b/artiq/gateware/rtio/core.py @@ -334,9 +334,9 @@ class _KernelCSRs(AutoCSR): self.chan_sel = CSRStorage(chan_sel_width) if data_width: - self.o_data = CSRStorage(data_width) + self.o_data = CSRStorage(data_width, write_from_dev=True) if address_width: - self.o_address = CSRStorage(address_width) + self.o_address = CSRStorage(address_width, write_from_dev=True) self.o_timestamp = CSRStorage(full_ts_width) self.o_we = CSR() self.o_status = CSRStatus(5) @@ -498,5 +498,13 @@ class RTIO(Module): << fine_ts_width) ) + # Auto clear/zero pad event data + self.comb += [ + self.kcsrs.o_data.dat_w.eq(0), + self.kcsrs.o_data.we.eq(self.kcsrs.o_timestamp.re), + self.kcsrs.o_address.dat_w.eq(0), + self.kcsrs.o_address.we.eq(self.kcsrs.o_timestamp.re), + ] + def get_csrs(self): return self.kcsrs.get_csrs()