diff --git a/artiq/gateware/drtio/transceiver/gtx_7series.py b/artiq/gateware/drtio/transceiver/gtx_7series.py
index 61e9287a7..8653dbe33 100644
--- a/artiq/gateware/drtio/transceiver/gtx_7series.py
+++ b/artiq/gateware/drtio/transceiver/gtx_7series.py
@@ -208,7 +208,7 @@ class RXSynchronizer(Module, AutoCSR):
     Xilinx scriptures (when existent) and should be constant for a given design
     placement.
     """
-    def __init__(self, rtio_clk_freq):
+    def __init__(self, rtio_clk_freq, initial_phase=0.0):
         self.phase_shift = CSR()
         self.phase_shift_done = CSRStatus()
 
@@ -228,6 +228,7 @@ class RXSynchronizer(Module, AutoCSR):
 
                 p_CLKFBOUT_MULT_F=mmcm_mult,
                 p_CLKOUT0_DIVIDE_F=mmcm_mult,
+                p_CLKOUT0_PHASE=intial_phase,
                 p_DIVCLK_DIVIDE=1,
 
                 # According to Xilinx, there is no guarantee of input/output