From 94b84ebe7cdb1d2d2f875d5bf8309397e191210c Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Tue, 2 Jan 2018 12:12:52 +0100 Subject: [PATCH] kc705_dds: add urukul spi/ttl channels --- artiq/examples/master/device_db.py | 51 ++++++++++++++++++++++++++--- artiq/gateware/targets/kc705_dds.py | 11 +++++++ doc/manual/core_device.rst | 48 +++++++++++++++++---------- 3 files changed, 89 insertions(+), 21 deletions(-) diff --git a/artiq/examples/master/device_db.py b/artiq/examples/master/device_db.py index b4c9c70ce..8d0b8c693 100644 --- a/artiq/examples/master/device_db.py +++ b/artiq/examples/master/device_db.py @@ -34,7 +34,7 @@ device_db = { "class": "DDSGroupAD9914", "arguments": { "sysclk": 3e9, - "first_dds_bus_channel": 32, + "first_dds_bus_channel": 39, "dds_bus_count": 2, "dds_channel_count": 3 } @@ -191,25 +191,68 @@ device_db = { "arguments": {"spi_device": "spi_zotino", "ldac_device": "ttl_zotino_ldac"} }, + "spi_urukul": { + "type": "local", + "module": "artiq.coredevice.spi", + "class": "SPIMaster", + "arguments": {"channel": 32} + }, + "ttl_urukul_io_update": { + "type": "local", + "module": "artiq.coredevice.ttl", + "class": "TTLOut", + "arguments": {"channel": 33} + }, + "ttl_urukul_dds_reset": { + "type": "local", + "module": "artiq.coredevice.ttl", + "class": "TTLOut", + "arguments": {"channel": 34} + }, + "ttl_urukul_sw0": { + "type": "local", + "module": "artiq.coredevice.ttl", + "class": "TTLOut", + "arguments": {"channel": 35} + }, + "ttl_urukul_sw1": { + "type": "local", + "module": "artiq.coredevice.ttl", + "class": "TTLOut", + "arguments": {"channel": 36} + }, + "ttl_urukul_sw2": { + "type": "local", + "module": "artiq.coredevice.ttl", + "class": "TTLOut", + "arguments": {"channel": 37} + }, + "ttl_urukul_sw3": { + "type": "local", + "module": "artiq.coredevice.ttl", + "class": "TTLOut", + "arguments": {"channel": 38} + }, + # AD9914 DDS "dds0": { "type": "local", "module": "artiq.coredevice.dds", "class": "DDSChannelAD9914", - "arguments": {"bus_channel": 32, "channel": 0}, + "arguments": {"bus_channel": 39, "channel": 0}, "comment": "Comments work in DDS panel as well" }, "dds1": { "type": "local", "module": "artiq.coredevice.dds", "class": "DDSChannelAD9914", - "arguments": {"bus_channel": 32, "channel": 1} + "arguments": {"bus_channel": 39, "channel": 1} }, "dds2": { "type": "local", "module": "artiq.coredevice.dds", "class": "DDSChannelAD9914", - "arguments": {"bus_channel": 32, "channel": 2} + "arguments": {"bus_channel": 39, "channel": 2} }, # Controllers diff --git a/artiq/gateware/targets/kc705_dds.py b/artiq/gateware/targets/kc705_dds.py index ce0a4deed..47b1fb6f5 100755 --- a/artiq/gateware/targets/kc705_dds.py +++ b/artiq/gateware/targets/kc705_dds.py @@ -353,6 +353,17 @@ class NIST_CLOCK(_NIST_Ions): self.submodules += dac_monitor sdac_phy.probes.extend(dac_monitor.probes) + phy = spi.SPIMaster(self.platform.request("urukul_spi_p"), + self.platform.request("urukul_spi_n")) + self.submodules += phy + rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4)) + + for signal in "io_update dds_reset sw0 sw1 sw2 sw3".split(): + pads = platform.request("urukul_{}".format(signal)) + phy = ttl_serdes_7series.Output_8X(pads.p, pads.n) + self.submodules += phy + rtio_channels.append(rtio.Channel.from_phy(phy)) + phy = dds.AD9914(platform.request("dds"), 11, onehot=True) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, diff --git a/doc/manual/core_device.rst b/doc/manual/core_device.rst index ed5eaf448..43f787eeb 100644 --- a/doc/manual/core_device.rst +++ b/doc/manual/core_device.rst @@ -76,28 +76,42 @@ With the CLOCK hardware, the TTL lines are mapped as follows: +--------------------+-----------------------+--------------+ | 31 | ZOTINO_LDAC | Output | +--------------------+-----------------------+--------------+ +| 33 | URUKUL_IO_UPDATE | Output | ++--------------------+-----------------------+--------------+ +| 34 | URUKUL_DDS_RESET | Output | ++--------------------+-----------------------+--------------+ +| 35 | URUKUL_SW0 | Output | ++--------------------+-----------------------+--------------+ +| 36 | URUKUL_SW1 | Output | ++--------------------+-----------------------+--------------+ +| 37 | URUKUL_SW2 | Output | ++--------------------+-----------------------+--------------+ +| 38 | URUKUL_SW3 | Output | ++--------------------+-----------------------+--------------+ The board has RTIO SPI buses mapped as follows: -+--------------+--------------+--------------+--------------+------------+ -| RTIO channel | CS_N | MOSI | MISO | CLK | -+==============+==============+==============+==============+============+ -| 22 | AMS101_CS_N | AMS101_MOSI | | AMS101_CLK | -+--------------+--------------+--------------+--------------+------------+ -| 23 | SPI0_CS_N | SPI0_MOSI | SPI0_MISO | SPI0_CLK | -+--------------+--------------+--------------+--------------+------------+ -| 24 | SPI1_CS_N | SPI1_MOSI | SPI1_MISO | SPI1_CLK | -+--------------+--------------+--------------+--------------+------------+ -| 25 | SPI2_CS_N | SPI2_MOSI | SPI2_MISO | SPI2_CLK | -+--------------+--------------+--------------+--------------+------------+ -| 26 | MMC_SPI_CS_N | MMC_SPI_MOSI | MMC_SPI_MISO | MMC_SPI_CLK| -+--------------+--------------+--------------+--------------+------------+ -| 30 | ZOTINO_CS_N | ZOTINO_MOSI | ZOTINO_MISO | ZOTINO_CLK | -+--------------+--------------+--------------+--------------+------------+ ++--------------+------------------+--------------+--------------+------------+ +| RTIO channel | CS_N | MOSI | MISO | CLK | ++==============+==================+==============+==============+============+ +| 22 | AMS101_CS_N | AMS101_MOSI | | AMS101_CLK | ++--------------+------------------+--------------+--------------+------------+ +| 23 | SPI0_CS_N | SPI0_MOSI | SPI0_MISO | SPI0_CLK | ++--------------+------------------+--------------+--------------+------------+ +| 24 | SPI1_CS_N | SPI1_MOSI | SPI1_MISO | SPI1_CLK | ++--------------+------------------+--------------+--------------+------------+ +| 25 | SPI2_CS_N | SPI2_MOSI | SPI2_MISO | SPI2_CLK | ++--------------+------------------+--------------+--------------+------------+ +| 26 | MMC_SPI_CS_N | MMC_SPI_MOSI | MMC_SPI_MISO | MMC_SPI_CLK| ++--------------+------------------+--------------+--------------+------------+ +| 30 | ZOTINO_CS_N | ZOTINO_MOSI | ZOTINO_MISO | ZOTINO_CLK | ++--------------+------------------+--------------+--------------+------------+ +| 32 | URUKUL_CS_N[0:2] | URUKUL_MOSI | URUKUL_MISO | URUKUL_CLK | ++--------------+------------------+--------------+--------------+------------+ -The DDS bus is on channel 32. +The DDS bus is on channel 39. -This configuration supports a Zotino connected to the KC705 FMC HPC through a FMC DIO 32ch LVDS v1.2 and a VHDCI breakout board rev 1.0. On the VHDCI breakout board, the VHDCI cable to the KC705 should be plugged into to the bottom connector, and the EEM cable to the Zotino should be connected to J41. +This configuration supports a Zotino and/or an Urukul connected to the KC705 FMC HPC through a FMC DIO 32ch LVDS v1.2 and a VHDCI breakout board rev 1.0 or rev 1.1. On the VHDCI breakout board, the VHDCI cable to the KC705 should be plugged into to the bottom connector. The EEM cable to the Zotino should be connected to J41 and the EEM cables to Urukul to J42 and J43. The shift registers on the FMC card should be configured to set the directions of its LVDS buffers, using :mod:`artiq.coredevice.shiftreg`.