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jdcg: fix missing JESD reset & JDAC re-init

This commit is contained in:
Harry Ho 2021-12-15 17:52:37 +08:00 committed by Sébastien Bourdeauducq
parent dc411d55be
commit 949917cc9c
1 changed files with 3 additions and 1 deletions
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4
artiq/firmware/satman/jdcg.rs
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@ -140,7 +140,7 @@ pub mod jdac {
pub mod jesd204sync { pub mod jesd204sync {
use board_misoc::{csr, clock, config}; use board_misoc::{csr, clock, config};
use super::jdac; use super::{jdac, jesd};
use super::super::jdac_common; use super::super::jdac_common;
const HMC7043_ANALOG_DELAY_RANGE: u8 = 24; const HMC7043_ANALOG_DELAY_RANGE: u8 = 24;
@ -423,6 +423,8 @@ pub mod jesd204sync {
} }
warn!("SYSREF test failed, retrying..."); warn!("SYSREF test failed, retrying...");
jdac::basic_request(0, jdac_common::DDMTD_INIT, 0)?; jdac::basic_request(0, jdac_common::DDMTD_INIT, 0)?;
jesd::reset(false);
let _ = jdac::init();
} else { break } } else { break }
} }