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spi: give wb-reads a register level

This commit is contained in:
Robert Jördens 2016-07-31 14:53:19 +02:00
parent b5e52e9870
commit 92f3757c74
1 changed files with 5 additions and 3 deletions
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8
artiq/gateware/spi.py
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@ -303,9 +303,6 @@ class SPIMaster(Module):
data_write = Signal.like(spi.reg.data) data_write = Signal.like(spi.reg.data)
self.comb += [ self.comb += [
bus.dat_r.eq(
Array([data_read, xfer.raw_bits(), config.raw_bits()
])[bus.adr]),
spi.start.eq(pending & (~spi.cs | spi.done)), spi.start.eq(pending & (~spi.cs | spi.done)),
spi.clk_phase.eq(config.clk_phase), spi.clk_phase.eq(config.clk_phase),
spi.reg.lsb.eq(config.lsb_first), spi.reg.lsb.eq(config.lsb_first),
@ -330,6 +327,11 @@ class SPIMaster(Module):
# d) writing to data register and pending and swapping buffers # d) writing to data register and pending and swapping buffers
bus.ack.eq(bus.cyc & bus.stb & bus.ack.eq(bus.cyc & bus.stb &
(~bus.we | (bus.adr != 0) | ~pending | spi.done)), (~bus.we | (bus.adr != 0) | ~pending | spi.done)),
If(bus.cyc & bus.stb,
bus.dat_r.eq(
Array([data_read, xfer.raw_bits(), config.raw_bits()
])[bus.adr]),
),
If(bus.ack, If(bus.ack,
bus.ack.eq(0), bus.ack.eq(0),
If(bus.we, If(bus.we,