From 92f3757c74e82498cc049430d45dfdd5e4d02a9e Mon Sep 17 00:00:00 2001
From: Robert Jordens <rj@m-labs.hk>
Date: Sun, 31 Jul 2016 14:53:19 +0200
Subject: [PATCH] spi: give wb-reads a register level

---
 artiq/gateware/spi.py | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/artiq/gateware/spi.py b/artiq/gateware/spi.py
index b62782fbf..0713bb3f0 100644
--- a/artiq/gateware/spi.py
+++ b/artiq/gateware/spi.py
@@ -303,9 +303,6 @@ class SPIMaster(Module):
         data_write = Signal.like(spi.reg.data)
 
         self.comb += [
-            bus.dat_r.eq(
-                Array([data_read, xfer.raw_bits(), config.raw_bits()
-                       ])[bus.adr]),
             spi.start.eq(pending & (~spi.cs | spi.done)),
             spi.clk_phase.eq(config.clk_phase),
             spi.reg.lsb.eq(config.lsb_first),
@@ -330,6 +327,11 @@ class SPIMaster(Module):
             # d) writing to data register and pending and swapping buffers
             bus.ack.eq(bus.cyc & bus.stb &
                        (~bus.we | (bus.adr != 0) | ~pending | spi.done)),
+            If(bus.cyc & bus.stb,
+                bus.dat_r.eq(
+                    Array([data_read, xfer.raw_bits(), config.raw_bits()
+                           ])[bus.adr]),
+            ),
             If(bus.ack,
                 bus.ack.eq(0),
                 If(bus.we,