mirror of https://github.com/m-labs/artiq.git
38 lines
1.2 KiB
Python
38 lines
1.2 KiB
Python
from migen import *
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from migen.genlib.fifo import *
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from artiq.gateware.rtio.sed import layouts
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__all__ = ["FIFOs"]
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class FIFOs(Module):
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def __init__(self, lane_count, fifo_depth, layout_payload, mode):
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seqn_width = layouts.seqn_width(lane_count, fifo_depth)
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self.input = [Record(layouts.fifo_ingress(seqn_width, layout_payload))
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for _ in range(lane_count)]
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self.output = [Record(layouts.fifo_egress(seqn_width, layout_payload))
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for _ in range(lane_count)]
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if mode == "sync":
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fifo_cls = SyncFIFOBuffered
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elif mode == "async":
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fifo_cls = AsyncFIFO
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else:
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raise ValueError
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for input, output in zip(self.input, self.output):
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fifo = fifo_cls(layout_len(layout_payload), fifo_depth)
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self.submodules += fifo
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self.comb += [
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fifo.din.eq(input.payload.raw_bits()),
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fifo.we.eq(input.we),
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input.writable.eq(fifo.writable),
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output.payload.raw_bits().eq(fifo.dout),
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output.readable.eq(fifo.readable),
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fifo.re.eq(output.re)
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]
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