From 929a7650a8280462bf8c767bd27409a7973b07b2 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 26 Oct 2016 22:03:44 +0800 Subject: [PATCH] drtio: fixes --- artiq/gateware/drtio/iot.py | 11 ++++++----- artiq/gateware/drtio/rt_controller.py | 5 ++--- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/artiq/gateware/drtio/iot.py b/artiq/gateware/drtio/iot.py index d7ba41c78..21e362367 100644 --- a/artiq/gateware/drtio/iot.py +++ b/artiq/gateware/drtio/iot.py @@ -48,17 +48,18 @@ class IOT(Module): # FIFO write self.comb += fifo.we.eq(rt_packets.write_stb & (rt_packets.write_channel == n)) - self.sync += \ + self.sync += [ + If(rt_packets.write_overflow_ack, + rt_packets.write_overflow.eq(0)), + If(rt_packets.write_underflow_ack, + rt_packets.write_underflow.eq(0)), If(fifo.we, - If(rt_packets.write_overflow_ack, - rt_packets.write_overflow.eq(0)), If(~fifo.writable, rt_packets.write_overflow.eq(1)), - If(rt_packets.write_underflow_ack, - rt_packets.write_underflow.eq(0)), If(rt_packets.write_timestamp[max_fine_ts_width:] < (tsc + 4), rt_packets.write_underflow.eq(1) ) ) + ] if data_width: self.comb += fifo_in.data.eq(rt_packets.write_data) if address_width: diff --git a/artiq/gateware/drtio/rt_controller.py b/artiq/gateware/drtio/rt_controller.py index fca4d75f4..a7ba5f2b6 100644 --- a/artiq/gateware/drtio/rt_controller.py +++ b/artiq/gateware/drtio/rt_controller.py @@ -48,7 +48,7 @@ class RTController(Module): self.comb += [ rt_packets.tsc_value.eq( self.counter.value_rtio + tsc_correction), - self.kcsrs.set_time.r.eq(rt_packets.set_time_stb) + self.kcsrs.set_time.w.eq(rt_packets.set_time_stb) ] self.sync += [ If(rt_packets.set_time_ack, rt_packets.set_time_stb.eq(0)), @@ -98,8 +98,7 @@ class RTController(Module): cond_sequence_error = self.kcsrs.o_timestamp.storage < last_timestamps.dat_r cond_underflow = ((self.kcsrs.o_timestamp.storage[fine_ts_width:] - self.kcsrs.underflow_margin.storage[fine_ts_width:]) < self.counter.value_sys) - cond_fifo_emptied = ((last_timestamps.dat_r[fine_ts_width:] - < self.counter.value_sys - self.kcsrs.underflow_margin.storage[fine_ts_width:]) + cond_fifo_emptied = ((last_timestamps.dat_r[fine_ts_width:] < self.counter.value_sys) & (last_timestamps.dat_r != 0)) fsm.act("IDLE",