pipistrello: sys_clk 83 -> 75 MHz

This should close #341 once migen generates stable output.
2016-03-21 13:47:32 +01:00 · 2016-03-21 13:47:32 +01:00 · 8f54a1e619
parent 22cd12f721
commit 8f54a1e619
1 changed files with 1 additions and 0 deletions
--- a/artiq/gateware/targets/pipistrello.py
+++ b/artiq/gateware/targets/pipistrello.py
@ -147,6 +147,7 @@ class NIST_QC1(BaseSoC, AMPSoC):
                         l2_size=64*1024,
                         with_timer=False,
                         ident=artiq_version,
+                         clk_freq=75*1000*1000,
                         **kwargs)
        AMPSoC.__init__(self)