From 8f54a1e6194733ef39859a408cd4ff2564e4cf5d Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Mon, 21 Mar 2016 13:47:32 +0100 Subject: [PATCH] pipistrello: sys_clk 83 -> 75 MHz This should close #341 once migen generates stable output. --- artiq/gateware/targets/pipistrello.py | 1 + 1 file changed, 1 insertion(+) diff --git a/artiq/gateware/targets/pipistrello.py b/artiq/gateware/targets/pipistrello.py index 2b2c7de65..6a6d1366d 100755 --- a/artiq/gateware/targets/pipistrello.py +++ b/artiq/gateware/targets/pipistrello.py @@ -147,6 +147,7 @@ class NIST_QC1(BaseSoC, AMPSoC): l2_size=64*1024, with_timer=False, ident=artiq_version, + clk_freq=75*1000*1000, **kwargs) AMPSoC.__init__(self)