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serwb: adapt test

This commit is contained in:
Florent Kermarrec 2018-04-17 19:21:53 +02:00
parent 20ccc9d82f
commit 8edf4541d6
1 changed files with 26 additions and 11 deletions
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37
artiq/gateware/test/serwb/test_serwb_core.py
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@ -6,6 +6,7 @@ from migen import *
from artiq.gateware.serwb import scrambler from artiq.gateware.serwb import scrambler
from artiq.gateware.serwb import core from artiq.gateware.serwb import core
from misoc.interconnect import stream
from misoc.interconnect.wishbone import SRAM from misoc.interconnect.wishbone import SRAM
@ -35,9 +36,30 @@ class FakeSerdes(Module):
class FakePHY(Module): class FakePHY(Module):
def __init__(self): def __init__(self):
self.sink = sink = stream.Endpoint([("data", 32)])
self.source = source = stream.Endpoint([("data", 32)])
# # #
self.submodules.init = FakeInit() self.submodules.init = FakeInit()
self.submodules.serdes = FakeSerdes() self.submodules.serdes = FakeSerdes()
# tx dataflow
self.comb += \
If(self.init.ready,
sink.ack.eq(self.serdes.tx_ce),
If(sink.stb,
self.serdes.tx_d.eq(sink.data)
)
)
# rx dataflow
self.comb += \
If(self.init.ready,
source.stb.eq(self.serdes.rx_ce),
source.data.eq(self.serdes.rx_d)
)
class DUTScrambler(Module): class DUTScrambler(Module):
def __init__(self): def __init__(self):
@ -47,15 +69,15 @@ class DUTScrambler(Module):
class DUTCore(Module): class DUTCore(Module):
def __init__(self, **kwargs): def __init__(self):
# wishbone slave # wishbone slave
phy_slave = FakePHY() phy_slave = FakePHY()
serwb_slave = core.SERWBCore(phy_slave, int(1e6), "slave", **kwargs) serwb_slave = core.SERWBCore(phy_slave, int(1e6), "slave")
self.submodules += phy_slave, serwb_slave self.submodules += phy_slave, serwb_slave
# wishbone master # wishbone master
phy_master = FakePHY() phy_master = FakePHY()
serwb_master = core.SERWBCore(phy_master, int(1e6), "master", **kwargs) serwb_master = core.SERWBCore(phy_master, int(1e6), "master")
self.submodules += phy_master, serwb_master self.submodules += phy_master, serwb_master
# connect phy # connect phy
@ -130,14 +152,7 @@ class TestSERWBCore(unittest.TestCase):
if datas_r[i] != datas_w[i]: if datas_r[i] != datas_w[i]:
dut.errors += 1 dut.errors += 1
# scrambling off dut = DUTCore()
dut = DUTCore(with_scrambling=False)
dut.errors = 0
run_simulation(dut, generator(dut))
self.assertEqual(dut.errors, 0)
# scrambling on
dut = DUTCore(with_scrambling=True)
dut.errors = 0 dut.errors = 0
run_simulation(dut, generator(dut)) run_simulation(dut, generator(dut))
self.assertEqual(dut.errors, 0) self.assertEqual(dut.errors, 0)