mirror of https://github.com/m-labs/artiq.git
kasli: remove leftover debug print
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@ -779,8 +779,6 @@ class USTC(_StandaloneBase):
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self.submodules += phy
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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rtio_channels.append(rtio.Channel.from_phy(phy))
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print(len(rtio_channels))
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self.config["HAS_RTIO_LOG"] = None
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.LogChannel())
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rtio_channels.append(rtio.LogChannel())
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