mirror of https://github.com/m-labs/artiq.git
Added support for HVAMP_8CH (#1741)
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@ -19,6 +19,8 @@ Highlights:
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- Expose the DAC coarse mixer and ``sif_sync``
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- Exposes upconverter calibration and enabling/disabling of upconverter LO & RF outputs.
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* ``get()``, ``get_mu()``, ``get_att()``, and ``get_att_mu()`` functions added for AD9910 and AD9912
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* New hardware support:
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- HVAMP_8CH 8 channel HV amplifier for Fastino / Zotino
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Breaking changes:
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@ -127,7 +127,7 @@
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"properties": {
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"type": {
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"type": "string",
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"enum": ["dio", "urukul", "novogorny", "sampler", "suservo", "zotino", "grabber", "mirny", "fastino", "phaser"]
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"enum": ["dio", "urukul", "novogorny", "sampler", "suservo", "zotino", "grabber", "mirny", "fastino", "phaser", "hvamp"]
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},
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"board": {
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"type": "string"
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@ -455,6 +455,28 @@
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},
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"required": ["ports"]
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}
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}, {
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"title": "HVAmp",
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"if": {
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"properties": {
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"type": {
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"const": "hvamp"
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}
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}
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},
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"then": {
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"properties": {
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"ports": {
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"type": "array",
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"items": {
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"type": "integer"
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},
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"minItems": 1,
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"maxItems": 1
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}
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},
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"required": ["ports"]
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}
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}]
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}
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}
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@ -515,6 +515,21 @@ class PeripheralManager:
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channel=rtio_offset)
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return 5
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def process_hvamp(self, rtio_offset, peripheral):
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hvamp_name = self.get_name("hvamp")
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for i in range(8):
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self.gen("""
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device_db["ttl_{name}_sw{ch}"] = {{
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {{"channel": 0x{channel:06x}}}
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}}""",
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name=hvamp_name,
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ch=i,
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channel=rtio_offset+i)
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return 8
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def process(self, rtio_offset, peripheral):
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processor = getattr(self, "process_"+str(peripheral["type"]))
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return processor(rtio_offset, peripheral)
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@ -660,3 +660,24 @@ class Phaser(_EEM):
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rtio.Channel.from_phy(phy.ch1.frequency),
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rtio.Channel.from_phy(phy.ch1.phase_amplitude),
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])
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class HVAmp(_EEM):
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@staticmethod
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def io(eem, iostandard):
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return [
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("hvamp{}_out_en".format(eem), i,
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Subsignal("p", Pins(_eem_pin(eem, i, "p"))),
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Subsignal("n", Pins(_eem_pin(eem, i, "n"))),
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iostandard(eem)
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) for i in range(8)]
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@classmethod
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def add_std(cls, target, eem, ttl_out_cls, iostandard=default_iostandard):
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cls.add_extension(target, eem, iostandard=iostandard)
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for i in range(8):
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pads = target.platform.request("hvamp{}_out_en".format(eem), i)
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phy = ttl_out_cls(pads.p, pads.n)
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target.submodules += phy
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target.rtio_channels.append(rtio.Channel.from_phy(phy))
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@ -110,6 +110,13 @@ def peripheral_phaser(module, peripheral, **kwargs):
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eem.Phaser.add_std(module, peripheral["ports"][0], **kwargs)
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def peripheral_hvamp(module, peripheral, **kwargs):
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if len(peripheral["ports"]) != 1:
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raise ValueError("wrong number of ports")
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eem.HVAmp.add_std(module, peripheral["ports"][0],
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ttl_simple.Output, **kwargs)
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peripheral_processors = {
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"dio": peripheral_dio,
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"urukul": peripheral_urukul,
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@ -121,6 +128,7 @@ peripheral_processors = {
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"mirny": peripheral_mirny,
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"fastino": peripheral_fastino,
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"phaser": peripheral_phaser,
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"hvamp": peripheral_hvamp,
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}
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