diff --git a/RELEASE_NOTES.rst b/RELEASE_NOTES.rst
index 37af7ed33..862ed148b 100644
--- a/RELEASE_NOTES.rst
+++ b/RELEASE_NOTES.rst
@@ -19,6 +19,8 @@ Highlights:
    - Expose the DAC coarse mixer and ``sif_sync``
    - Exposes upconverter calibration and enabling/disabling of upconverter LO & RF outputs.
 * ``get()``, ``get_mu()``, ``get_att()``, and ``get_att_mu()`` functions added for AD9910 and AD9912
+* New hardware support:
+   - HVAMP_8CH 8 channel HV amplifier for Fastino / Zotino
 
 Breaking changes:
 
diff --git a/artiq/coredevice/coredevice_generic.schema.json b/artiq/coredevice/coredevice_generic.schema.json
index 47319fe3e..64e4a9251 100644
--- a/artiq/coredevice/coredevice_generic.schema.json
+++ b/artiq/coredevice/coredevice_generic.schema.json
@@ -127,7 +127,7 @@
             "properties": {
                 "type": {
                     "type": "string",
-                    "enum": ["dio", "urukul", "novogorny", "sampler", "suservo", "zotino", "grabber", "mirny", "fastino", "phaser"]
+                    "enum": ["dio", "urukul", "novogorny", "sampler", "suservo", "zotino", "grabber", "mirny", "fastino", "phaser", "hvamp"]
                 },
                 "board": {
                     "type": "string"
@@ -455,6 +455,28 @@
                     },
                     "required": ["ports"]
                 }
+            }, {
+                "title": "HVAmp",
+                "if": {
+                    "properties": {
+                        "type": {
+                            "const": "hvamp"
+                        }
+                    }
+                },
+                "then": {
+                    "properties": {
+                        "ports": {
+                            "type": "array",
+                            "items": {
+                                "type": "integer"
+                            },
+                            "minItems": 1,
+                            "maxItems": 1
+                        }
+                    },
+                    "required": ["ports"]
+                }
             }]
         }
     }
diff --git a/artiq/frontend/artiq_ddb_template.py b/artiq/frontend/artiq_ddb_template.py
index 9d7359187..98b4bd5b9 100755
--- a/artiq/frontend/artiq_ddb_template.py
+++ b/artiq/frontend/artiq_ddb_template.py
@@ -515,6 +515,21 @@ class PeripheralManager:
             channel=rtio_offset)
         return 5
 
+    def process_hvamp(self, rtio_offset, peripheral):
+        hvamp_name = self.get_name("hvamp")
+        for i in range(8):
+            self.gen("""
+                device_db["ttl_{name}_sw{ch}"] = {{
+                    "type": "local",
+                    "module": "artiq.coredevice.ttl",
+                    "class": "TTLOut",
+                    "arguments": {{"channel": 0x{channel:06x}}}
+                }}""",
+                name=hvamp_name,
+                ch=i,
+                channel=rtio_offset+i)
+        return 8
+
     def process(self, rtio_offset, peripheral):
         processor = getattr(self, "process_"+str(peripheral["type"]))
         return processor(rtio_offset, peripheral)
diff --git a/artiq/gateware/eem.py b/artiq/gateware/eem.py
index 0180989de..7f5fe3fdf 100644
--- a/artiq/gateware/eem.py
+++ b/artiq/gateware/eem.py
@@ -660,3 +660,24 @@ class Phaser(_EEM):
             rtio.Channel.from_phy(phy.ch1.frequency),
             rtio.Channel.from_phy(phy.ch1.phase_amplitude),
         ])
+
+
+class HVAmp(_EEM):
+    @staticmethod
+    def io(eem, iostandard):
+        return [
+            ("hvamp{}_out_en".format(eem), i,
+                    Subsignal("p", Pins(_eem_pin(eem, i, "p"))),
+                    Subsignal("n", Pins(_eem_pin(eem, i, "n"))),
+                    iostandard(eem)
+            ) for i in range(8)]
+
+    @classmethod
+    def add_std(cls, target, eem, ttl_out_cls, iostandard=default_iostandard):
+        cls.add_extension(target, eem, iostandard=iostandard)
+
+        for i in range(8):
+            pads = target.platform.request("hvamp{}_out_en".format(eem), i)
+            phy = ttl_out_cls(pads.p, pads.n)
+            target.submodules += phy
+            target.rtio_channels.append(rtio.Channel.from_phy(phy))
diff --git a/artiq/gateware/eem_7series.py b/artiq/gateware/eem_7series.py
index bbd883a83..232150211 100644
--- a/artiq/gateware/eem_7series.py
+++ b/artiq/gateware/eem_7series.py
@@ -110,6 +110,13 @@ def peripheral_phaser(module, peripheral, **kwargs):
     eem.Phaser.add_std(module, peripheral["ports"][0], **kwargs)
 
 
+def peripheral_hvamp(module, peripheral, **kwargs):
+    if len(peripheral["ports"]) != 1:
+        raise ValueError("wrong number of ports")
+    eem.HVAmp.add_std(module, peripheral["ports"][0], 
+        ttl_simple.Output, **kwargs)
+
+
 peripheral_processors = {
     "dio": peripheral_dio,
     "urukul": peripheral_urukul,
@@ -121,6 +128,7 @@ peripheral_processors = {
     "mirny": peripheral_mirny,
     "fastino": peripheral_fastino,
     "phaser": peripheral_phaser,
+    "hvamp": peripheral_hvamp,
 }