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artiq
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Merge branch 'master' of https://github.com/m-labs/artiq

This commit is contained in:
Sebastien Bourdeauducq 2015-02-06 21:57:08 +08:00
parent 5cec341f73 c97946a71c
commit 8979d9d5e7
2 changed files with 15 additions and 7 deletions
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16
.travis.yml
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@ -8,17 +8,16 @@ env:
- CC=gcc-4.7 - CC=gcc-4.7
- CXX=g++-4.7 - CXX=g++-4.7
- ARTIQ_NO_HARDWARE=1 - ARTIQ_NO_HARDWARE=1
- BUILD_SOC=0
- secure: "DUk/Ihg8KbbzEgPF0qrHqlxU8e8eET9i/BtzNvFddIGX4HP/P2qz0nk3cVkmjuWhqJXSbC22RdKME9qqPzw6fJwJ6dpJ3OR6dDmSd7rewavq+niwxu52PVa+yK8mL4yf1terM7QQ5tIRf+yUL9qGKrZ2xyvEuRit6d4cFep43Ws=" - secure: "DUk/Ihg8KbbzEgPF0qrHqlxU8e8eET9i/BtzNvFddIGX4HP/P2qz0nk3cVkmjuWhqJXSbC22RdKME9qqPzw6fJwJ6dpJ3OR6dDmSd7rewavq+niwxu52PVa+yK8mL4yf1terM7QQ5tIRf+yUL9qGKrZ2xyvEuRit6d4cFep43Ws="
before_install: before_install:
- if echo "$TRAVIS_COMMIT_MSG" | grep -q "\[soc\]"; then BUILD_SOC=1; fi
- if [ $TRAVIS_PULL_REQUEST != false ]; then BUILD_SOC=0; fi
- ./.travis/get-toolchain.sh - ./.travis/get-toolchain.sh
- ./.travis/get-xilinx.sh - if [ $BUILD_SOC -ne 0 ]; then ./.travis/get-xilinx.sh; fi
- ./.travis/get-anaconda.sh pip coverage numpy scipy sphinx h5py pyserial dateutil - ./.travis/get-anaconda.sh pip coverage numpy scipy sphinx h5py pyserial dateutil
- source $HOME/miniconda/bin/activate py34 - source $HOME/miniconda/bin/activate py34
- sudo apt-get install --force-yes -y iverilog - ./.travis/get-misoc.sh
- pip install --src . -e 'git+https://github.com/m-labs/migen.git@master#egg=migen'
- mkdir vpi
- iverilog-vpi --name=vpi/migensim migen/vpi/main.c migen/vpi/ipc.c
- git clone --recursive https://github.com/m-labs/misoc
- pip install --src . -e 'git+https://github.com/nist-ionstorage/llvmlite.git@artiq#egg=llvmlite' - pip install --src . -e 'git+https://github.com/nist-ionstorage/llvmlite.git@artiq#egg=llvmlite'
- pip install coveralls - pip install coveralls
install: install:
@ -28,7 +27,7 @@ script:
- make -C doc/manual html - make -C doc/manual html
- cd misoc; python make.py -X ../soc -t artiq build-headers build-bios; cd .. - cd misoc; python make.py -X ../soc -t artiq build-headers build-bios; cd ..
- make -C soc/runtime - make -C soc/runtime
- cd misoc; python make.py -X ../soc -t artiq build-bitstream; cd .. - if [ $BUILD_SOC -ne 0 ]; then cd misoc; python make.py -X ../soc -t artiq build-bitstream; cd ..; fi
after_success: after_success:
coveralls coveralls
notifications: notifications:
@ -36,6 +35,9 @@ notifications:
irc: irc:
channels: channels:
- chat.freenode.net#m-labs - chat.freenode.net#m-labs
template:
- "%{repository}#%{build_number} (%{branch} - %{commit} : %{author}): %{message}"
- "Build details : %{build_url}"
webhooks: webhooks:
urls: urls:
- https://webhooks.gitter.im/e/d26782523952bfa53814 - https://webhooks.gitter.im/e/d26782523952bfa53814

6
.travis/get-misoc.sh Executable file
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@ -0,0 +1,6 @@
#!/bin/sh
sudo apt-get install --force-yes -y iverilog
pip install --src . -e 'git+https://github.com/m-labs/migen.git@master#egg=migen'
mkdir vpi && iverilog-vpi --name=vpi/migensim migen/vpi/main.c migen/vpi/ipc.c
git clone --recursive https://github.com/m-labs/misoc