M-Labs/artiq
2
0
Fork 2
mirror of https://github.com/m-labs/artiq.git synced 2024-12-19 00:16:29 +08:00
Code Issues Projects Releases Wiki Activity

wrpll.ddmtd: fix first edge deglitcher

Browse Source 
The blind counter should be held in reset whenever the input is high,
not just when there is a rising edge (otherwise the counter runs down
during the main pulse and can then re-trigger on jitter from the falling edge)
This commit is contained in:
hartytp 2020-10-06 15:42:37 +01:00 committed by Sebastien Bourdeauducq
parent f3cd0fc675
commit 85bb641917
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
artiq/gateware/drtio/wrpll/ddmtd.py
View File

@ -83,7 +83,7 @@ class DDMTDDeglitcherFirstEdge(Module):
blind_counter = Signal(max=blind_period) blind_counter = Signal(max=blind_period)
self.sync.helper += [ self.sync.helper += [
If(blind_counter != 0, blind_counter.eq(blind_counter - 1)), If(blind_counter != 0, blind_counter.eq(blind_counter - 1)),
If(rising, blind_counter.eq(blind_period - 1)), If(input_signal_r, blind_counter.eq(blind_period - 1)),
self.detect.eq(rising & (blind_counter == 0)) self.detect.eq(rising & (blind_counter == 0))
] ]