disable DRTIO-over-EEM OSERDES until clock is stable

This asserts OOB reset on EFC.

artiq/firmware/runtime/rtio_clocking.rs

@@ -267,6 +267,9 @@ pub fn init() {
             // enable TX after the reboot, with stable clock
             unsafe {
                 csr::gt_drtio::txenable_write(0xffffffffu32 as _);
+
+                #[cfg(has_drtio_eem)]
+                csr::eem_transceiver::txenable_write(0xffffffffu32 as _);
             }
         }
     }

artiq/firmware/satman/main.rs

@@ -556,6 +556,11 @@ pub extern fn main() -> i32 {
         csr::gt_drtio::txenable_write(0xffffffffu32 as _);
     }
 
+    #[cfg(has_drtio_eem)]
+    unsafe {
+        csr::eem_transceiver::txenable_write(0xffffffffu32 as _);
+    }
+
     init_rtio_crg();
 
     #[cfg(has_drtio_eem)]

artiq/gateware/drtio/transceiver/eem_serdes.py

@@ -109,6 +109,8 @@ class TXSerdes(Module):
         ser_out = [ Signal() for _ in range(4) ]
         t_out = [ Signal() for _ in range(4) ]
 
+        self.ext_rst = Signal()
+
         for i in range(4):
             self.specials += [
                 # Serializer
@@ -118,7 +120,7 @@ class TXSerdes(Module):
                     p_INIT_OQ=0b00000,
                     o_OQ=ser_out[i],
                     o_TQ=t_out[i],
-                    i_RST=ResetSignal(),
+                    i_RST=ResetSignal() | self.ext_rst,
                     i_CLK=ClockSignal("sys5x"),
                     i_CLKDIV=ClockSignal(),
                     i_D1=self.txdata[i][0],
@@ -529,3 +531,6 @@ class EEMSerdes(Module, TransceiverInterface, AutoCSR):
         self.rst.attr.add("no_retiming")
 
         TransceiverInterface.__init__(self, channel_interfaces, async_rx=False)
+
+        for tx_en, serdes in zip(self.txenable.storage, serdes_list):
+            self.comb += serdes.tx_serdes.ext_rst.eq(~tx_en)