mirror of https://github.com/m-labs/artiq.git
kasli: add missing cri_con to Satellite
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@ -899,6 +899,7 @@ class _SatelliteBase(BaseSoC):
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[self.drtiosat.cri],
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[self.drtiosat.cri],
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[self.local_io.cri] + self.drtio_cri,
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[self.local_io.cri] + self.drtio_cri,
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mode="sync", enable_routing=True)
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mode="sync", enable_routing=True)
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self.csr_devices.append("cri_con")
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class Master(_MasterBase):
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class Master(_MasterBase):
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