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artiq
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firmware: add drtioaux routing packets

pull/1212/head
Sebastien Bourdeauducq 2018-09-09 22:44:25 +08:00
parent 7ae44f3417
commit 014cfd8dbd
1 changed files with 30 additions and 0 deletions
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30
artiq/firmware/libproto_artiq/drtioaux_proto.rs
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@ -28,6 +28,10 @@ pub enum Packet {
RtioErrorCollisionReply { channel: u16 },
RtioErrorBusyReply { channel: u16 },
RoutingSetPath { destination: u8, hops: [u8; 32] },
RoutingSetRank { rank: u8 },
RoutingAck,
MonitorRequest { channel: u16, probe: u8 },
MonitorReply { value: u32 },
InjectionRequest { channel: u16, overrd: u8, value: u8 },
@ -75,6 +79,20 @@ impl Packet {
channel: reader.read_u16()?
},
0x30 => {
let destination = reader.read_u8()?;
let mut hops = [0; 32];
reader.read_exact(&mut hops)?;
Packet::RoutingSetPath {
destination: destination,
hops: hops
}
},
0x31 => Packet::RoutingSetRank {
rank: reader.read_u8()?
},
0x32 => Packet::RoutingAck,
0x40 => Packet::MonitorRequest {
channel: reader.read_u16()?,
probe: reader.read_u8()?
@ -185,6 +203,18 @@ impl Packet {
writer.write_u16(channel)?;
},
Packet::RoutingSetPath { destination, hops } => {
writer.write_u8(0x30)?;
writer.write_u8(destination)?;
writer.write_all(&hops)?;
},
Packet::RoutingSetRank { rank } => {
writer.write_u8(0x31)?;
writer.write_u8(rank)?;
},
Packet::RoutingAck =>
writer.write_u8(0x32)?,
Packet::MonitorRequest { channel, probe } => {
writer.write_u8(0x40)?;
writer.write_u16(channel)?;