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drtio: do not reset remote TSC on reset command

This commit is contained in:
Sebastien Bourdeauducq 2016-11-24 00:09:53 +08:00
parent 0d5f962d0c
commit 7cd27abaa6
2 changed files with 11 additions and 10 deletions
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4
artiq/gateware/drtio/core.py
View File

@ -27,8 +27,8 @@ class DRTIOSatellite(Module):
self.submodules.rt_packets = ClockDomainsRenamer("rtio")( self.submodules.rt_packets = ClockDomainsRenamer("rtio")(
rt_packets.RTPacketSatellite(link_layer_sync)) rt_packets.RTPacketSatellite(link_layer_sync))
self.submodules.iot = ClockDomainsRenamer("rio")( self.submodules.iot = iot.IOT(
iot.IOT(self.rt_packets, channels, fine_ts_width, full_ts_width)) self.rt_packets, channels, fine_ts_width, full_ts_width)
self.clock_domains.cd_rio = ClockDomain() self.clock_domains.cd_rio = ClockDomain()
self.clock_domains.cd_rio_phy = ClockDomain() self.clock_domains.cd_rio_phy = ClockDomain()

17
artiq/gateware/drtio/iot.py
View File

@ -8,7 +8,7 @@ from artiq.gateware.rtio import rtlink
class IOT(Module): class IOT(Module):
def __init__(self, rt_packets, channels, max_fine_ts_width, full_ts_width): def __init__(self, rt_packets, channels, max_fine_ts_width, full_ts_width):
tsc = Signal(full_ts_width - max_fine_ts_width) tsc = Signal(full_ts_width - max_fine_ts_width)
self.sync += \ self.sync.rtio += \
If(rt_packets.tsc_load, If(rt_packets.tsc_load,
tsc.eq(rt_packets.tsc_value) tsc.eq(rt_packets.tsc_value)
).Else( ).Else(
@ -30,7 +30,8 @@ class IOT(Module):
ev_layout.append(("address", address_width)) ev_layout.append(("address", address_width))
ev_layout.append(("timestamp", len(tsc) + fine_ts_width)) ev_layout.append(("timestamp", len(tsc) + fine_ts_width))
fifo = SyncFIFOBuffered(layout_len(ev_layout), channel.ofifo_depth) fifo = ClockDomainsRenamer("rio")(
SyncFIFOBuffered(layout_len(ev_layout), channel.ofifo_depth))
self.submodules += fifo self.submodules += fifo
fifo_in = Record(ev_layout) fifo_in = Record(ev_layout)
fifo_out = Record(ev_layout) fifo_out = Record(ev_layout)
@ -40,7 +41,7 @@ class IOT(Module):
] ]
# FIFO level # FIFO level
self.sync += \ self.sync.rio += \
If(rt_packets.fifo_space_update & If(rt_packets.fifo_space_update &
(rt_packets.fifo_space_channel == n), (rt_packets.fifo_space_channel == n),
rt_packets.fifo_space.eq(channel.ofifo_depth - fifo.level)) rt_packets.fifo_space.eq(channel.ofifo_depth - fifo.level))
@ -48,7 +49,7 @@ class IOT(Module):
# FIFO write # FIFO write
self.comb += fifo.we.eq(rt_packets.write_stb self.comb += fifo.we.eq(rt_packets.write_stb
& (rt_packets.write_channel == n)) & (rt_packets.write_channel == n))
self.sync += [ self.sync.rio += [
If(rt_packets.write_overflow_ack, If(rt_packets.write_overflow_ack,
rt_packets.write_overflow.eq(0)), rt_packets.write_overflow.eq(0)),
If(rt_packets.write_underflow_ack, If(rt_packets.write_underflow_ack,
@ -68,7 +69,7 @@ class IOT(Module):
rt_packets.write_timestamp[max_fine_ts_width-fine_ts_width:]) rt_packets.write_timestamp[max_fine_ts_width-fine_ts_width:])
# FIFO read # FIFO read
self.sync += [ self.sync.rio += [
fifo.re.eq(0), fifo.re.eq(0),
interface.stb.eq(0), interface.stb.eq(0),
If(fifo.readable & If(fifo.readable &
@ -78,8 +79,8 @@ class IOT(Module):
) )
] ]
if data_width: if data_width:
self.sync += interface.data.eq(fifo_out.data) self.sync.rio += interface.data.eq(fifo_out.data)
if address_width: if address_width:
self.sync += interface.address.eq(fifo_out.address) self.sync.rio += interface.address.eq(fifo_out.address)
if fine_ts_width: if fine_ts_width:
self.sync += interface.fine_ts.eq(fifo_out.timestamp[:fine_ts_width]) self.sync.rio += interface.fine_ts.eq(fifo_out.timestamp[:fine_ts_width])