From 7cd27abaa61aa03714ea4122aa2d84642e051273 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 24 Nov 2016 00:09:53 +0800 Subject: [PATCH] drtio: do not reset remote TSC on reset command --- artiq/gateware/drtio/core.py | 4 ++-- artiq/gateware/drtio/iot.py | 17 +++++++++-------- 2 files changed, 11 insertions(+), 10 deletions(-) diff --git a/artiq/gateware/drtio/core.py b/artiq/gateware/drtio/core.py index 995b0b137..b7d9698b8 100644 --- a/artiq/gateware/drtio/core.py +++ b/artiq/gateware/drtio/core.py @@ -27,8 +27,8 @@ class DRTIOSatellite(Module): self.submodules.rt_packets = ClockDomainsRenamer("rtio")( rt_packets.RTPacketSatellite(link_layer_sync)) - self.submodules.iot = ClockDomainsRenamer("rio")( - iot.IOT(self.rt_packets, channels, fine_ts_width, full_ts_width)) + self.submodules.iot = iot.IOT( + self.rt_packets, channels, fine_ts_width, full_ts_width) self.clock_domains.cd_rio = ClockDomain() self.clock_domains.cd_rio_phy = ClockDomain() diff --git a/artiq/gateware/drtio/iot.py b/artiq/gateware/drtio/iot.py index 21e362367..9b6ec2a83 100644 --- a/artiq/gateware/drtio/iot.py +++ b/artiq/gateware/drtio/iot.py @@ -8,7 +8,7 @@ from artiq.gateware.rtio import rtlink class IOT(Module): def __init__(self, rt_packets, channels, max_fine_ts_width, full_ts_width): tsc = Signal(full_ts_width - max_fine_ts_width) - self.sync += \ + self.sync.rtio += \ If(rt_packets.tsc_load, tsc.eq(rt_packets.tsc_value) ).Else( @@ -30,7 +30,8 @@ class IOT(Module): ev_layout.append(("address", address_width)) ev_layout.append(("timestamp", len(tsc) + fine_ts_width)) - fifo = SyncFIFOBuffered(layout_len(ev_layout), channel.ofifo_depth) + fifo = ClockDomainsRenamer("rio")( + SyncFIFOBuffered(layout_len(ev_layout), channel.ofifo_depth)) self.submodules += fifo fifo_in = Record(ev_layout) fifo_out = Record(ev_layout) @@ -40,7 +41,7 @@ class IOT(Module): ] # FIFO level - self.sync += \ + self.sync.rio += \ If(rt_packets.fifo_space_update & (rt_packets.fifo_space_channel == n), rt_packets.fifo_space.eq(channel.ofifo_depth - fifo.level)) @@ -48,7 +49,7 @@ class IOT(Module): # FIFO write self.comb += fifo.we.eq(rt_packets.write_stb & (rt_packets.write_channel == n)) - self.sync += [ + self.sync.rio += [ If(rt_packets.write_overflow_ack, rt_packets.write_overflow.eq(0)), If(rt_packets.write_underflow_ack, @@ -68,7 +69,7 @@ class IOT(Module): rt_packets.write_timestamp[max_fine_ts_width-fine_ts_width:]) # FIFO read - self.sync += [ + self.sync.rio += [ fifo.re.eq(0), interface.stb.eq(0), If(fifo.readable & @@ -78,8 +79,8 @@ class IOT(Module): ) ] if data_width: - self.sync += interface.data.eq(fifo_out.data) + self.sync.rio += interface.data.eq(fifo_out.data) if address_width: - self.sync += interface.address.eq(fifo_out.address) + self.sync.rio += interface.address.eq(fifo_out.address) if fine_ts_width: - self.sync += interface.fine_ts.eq(fifo_out.timestamp[:fine_ts_width]) + self.sync.rio += interface.fine_ts.eq(fifo_out.timestamp[:fine_ts_width])