diff --git a/artiq/gateware/rtio/phy/dds.py b/artiq/gateware/rtio/phy/dds.py
index 040a701f5..c19f3c588 100644
--- a/artiq/gateware/rtio/phy/dds.py
+++ b/artiq/gateware/rtio/phy/dds.py
@@ -6,7 +6,7 @@ from artiq.gateware.rtio.phy.wishbone import RT2WB
 
 class _AD9xxx(Module):
     def __init__(self, ftw_base, pads, nchannels, onehot=False, **kwargs):
-        self.submodules._ll = ClockDomainsRenamer("rio")(
+        self.submodules._ll = ClockDomainsRenamer("rio_phy")(
             ad9xxx.AD9xxx(pads, **kwargs))
         self.submodules._rt2wb = RT2WB(len(pads.a)+1, self._ll.bus)
         self.rtlink = self._rt2wb.rtlink
diff --git a/artiq/gateware/rtio/phy/spi.py b/artiq/gateware/rtio/phy/spi.py
index 92ab7a548..1882eb700 100644
--- a/artiq/gateware/rtio/phy/spi.py
+++ b/artiq/gateware/rtio/phy/spi.py
@@ -6,7 +6,7 @@ from artiq.gateware.rtio.phy.wishbone import RT2WB
 
 class SPIMaster(Module):
     def __init__(self, pads, **kwargs):
-        self.submodules._ll = ClockDomainsRenamer("rio")(
+        self.submodules._ll = ClockDomainsRenamer("rio_phy")(
             SPIMasterWB(pads, **kwargs))
         self.submodules._rt2wb = RT2WB(2, self._ll.bus)
         self.rtlink = self._rt2wb.rtlink