From 76fc63bbf77d2b2053201d0f4ca205623b937d63 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 22 Jun 2018 11:38:18 +0800 Subject: [PATCH] jesd204: use separate controls for reset and input buffer disable --- artiq/firmware/libboard_artiq/ad9154.rs | 3 ++- artiq/gateware/jesd204_tools.py | 5 +++-- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/artiq/firmware/libboard_artiq/ad9154.rs b/artiq/firmware/libboard_artiq/ad9154.rs index c4086ca02..a1549b601 100644 --- a/artiq/firmware/libboard_artiq/ad9154.rs +++ b/artiq/firmware/libboard_artiq/ad9154.rs @@ -36,7 +36,8 @@ fn read(addr: u16) -> u8 { fn jesd_unreset() { unsafe { - csr::ad9154_crg::jreset_write(0) + csr::ad9154_crg::ibuf_disable_write(0); + csr::ad9154_crg::jreset_write(0); } } diff --git a/artiq/gateware/jesd204_tools.py b/artiq/gateware/jesd204_tools.py index e467a87c9..0e35b055e 100644 --- a/artiq/gateware/jesd204_tools.py +++ b/artiq/gateware/jesd204_tools.py @@ -20,6 +20,7 @@ class UltrascaleCRG(Module, AutoCSR): fabric_freq = int(125e6) def __init__(self, platform, use_rtio_clock=False): + self.ibuf_disable = CSRStorage(reset=1) self.jreset = CSRStorage(reset=1) self.jref = Signal() self.refclk = Signal() @@ -29,7 +30,7 @@ class UltrascaleCRG(Module, AutoCSR): refclk_pads = platform.request("dac_refclk", 1) platform.add_period_constraint(refclk_pads.p, 1e9/self.refclk_freq) self.specials += [ - Instance("IBUFDS_GTE3", i_CEB=self.jreset.storage, p_REFCLK_HROW_CK_SEL=0b00, + Instance("IBUFDS_GTE3", i_CEB=self.ibuf_disable.storage, p_REFCLK_HROW_CK_SEL=0b00, i_I=refclk_pads.p, i_IB=refclk_pads.n, o_O=self.refclk, o_ODIV2=refclk2), AsyncResetSynchronizer(self.cd_jesd, self.jreset.storage), @@ -46,7 +47,7 @@ class UltrascaleCRG(Module, AutoCSR): self.specials += [ Instance("IBUFDS_IBUFDISABLE", p_USE_IBUFDISABLE="TRUE", p_SIM_DEVICE="ULTRASCALE", - i_IBUFDISABLE=self.jreset.storage, + i_IBUFDISABLE=self.ibuf_disable.storage, i_I=jref.p, i_IB=jref.n, o_O=jref_se), # SYSREF normally meets s/h at the FPGA, except during margin