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sayma: use GTP_CLK1 to clock DRTIO satellite transceiver 

This is required to get constant skew between the DRTIO transceiver clock
(which then generates the RTIO clock) and the siphaser reference clock.

Both the Si5324 and the RTM clock tree have non-deterministic in-to-out skew
at 150MHz due to dividers.
This commit is contained in:
Sebastien Bourdeauducq 2018-06-28 11:23:40 +08:00
parent a65721d649
commit 729ce58f98
2 changed files with 4 additions and 4 deletions
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6
artiq/firmware/satman/main.rs
View File

@ -270,13 +270,13 @@ pub extern fn main() -> i32 {
i2c::init(); i2c::init();
si5324::setup(&SI5324_SETTINGS, si5324::Input::Ckin1).expect("cannot initialize Si5324"); si5324::setup(&SI5324_SETTINGS, si5324::Input::Ckin1).expect("cannot initialize Si5324");
#[cfg(has_hmc830_7043)]
/* must be the first SPI init because of HMC830 SPI mode selection */
hmc830_7043::init().expect("cannot initialize HMC830/7043");
unsafe { unsafe {
csr::drtio_transceiver::stable_clkin_write(1); csr::drtio_transceiver::stable_clkin_write(1);
} }
#[cfg(has_hmc830_7043)]
/* must be the first SPI init because of HMC830 SPI mode selection */
hmc830_7043::init().expect("cannot initialize HMC830/7043");
#[cfg(has_ad9154)] #[cfg(has_ad9154)]
let mut ad9154_initialized = false; let mut ad9154_initialized = false;
#[cfg(has_allaki_atts)] #[cfg(has_allaki_atts)]

2
artiq/gateware/targets/sayma_amc.py
View File

@ -552,7 +552,7 @@ class Satellite(BaseSoC, RTMCommon):
self.comb += platform.request("sfp_tx_disable", 0).eq(0) self.comb += platform.request("sfp_tx_disable", 0).eq(0)
self.submodules.drtio_transceiver = gth_ultrascale.GTH( self.submodules.drtio_transceiver = gth_ultrascale.GTH(
clock_pads=platform.request("si5324_clkout"), clock_pads=platform.request("dac_refclk", 0),
data_pads=[platform.request("sfp", 0)], data_pads=[platform.request("sfp", 0)],
sys_clk_freq=self.clk_freq, sys_clk_freq=self.clk_freq,
rtio_clk_freq=rtio_clk_freq) rtio_clk_freq=rtio_clk_freq)