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grabber: add false path constraints

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This commit is contained in:
Sebastien Bourdeauducq 2018-07-10 14:28:23 +08:00
parent 6a77032fa5
commit 701c93d46c
1 changed files with 8 additions and 0 deletions
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8
artiq/gateware/eem.py
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@ -414,6 +414,14 @@ class Grabber(_EEM):
phy = grabber.Grabber(pads)
name = "grabber{}".format(len(target.grabber_csr_group))
setattr(target.submodules, name, phy)
target.platform.add_false_path_constraints(
target.crg.cd_sys.clk, phy.deserializer.cd_cl.clk)
# Avoid bogus s/h violations at the clock input being sampled
# by the ISERDES. This uses dynamic calibration.
target.platform.add_false_path_constraints(
pads.clk_p, phy.deserializer.cd_cl7x.clk)
target.grabber_csr_group.append(name)
target.csr_devices.append(name)
target.rtio_channels += [