From 701c93d46cf3c3695c155d9ee76e73b3c567cea6 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 10 Jul 2018 14:28:23 +0800 Subject: [PATCH] grabber: add false path constraints --- artiq/gateware/eem.py | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/artiq/gateware/eem.py b/artiq/gateware/eem.py index 2de10a145..8690d9930 100644 --- a/artiq/gateware/eem.py +++ b/artiq/gateware/eem.py @@ -414,6 +414,14 @@ class Grabber(_EEM): phy = grabber.Grabber(pads) name = "grabber{}".format(len(target.grabber_csr_group)) setattr(target.submodules, name, phy) + + target.platform.add_false_path_constraints( + target.crg.cd_sys.clk, phy.deserializer.cd_cl.clk) + # Avoid bogus s/h violations at the clock input being sampled + # by the ISERDES. This uses dynamic calibration. + target.platform.add_false_path_constraints( + pads.clk_p, phy.deserializer.cd_cl7x.clk) + target.grabber_csr_group.append(name) target.csr_devices.append(name) target.rtio_channels += [