rtio: support single-master CRI arbiter

2016-12-01 16:30:11 +08:00 · 2016-12-01 16:30:11 +08:00 · 6c97a97d8c
parent a318243083
commit 6c97a97d8c
1 changed files with 24 additions and 21 deletions
--- a/artiq/gateware/rtio/cri.py
+++ b/artiq/gateware/rtio/cri.py
@ -160,6 +160,9 @@ class CRIArbiter(Module):

        # # #

+        if len(masters) == 1:
+            self.comb += masters[0].connect(slave)
+        else:
            selected = Signal(max=len(masters))

            # mux master->slave signals