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phaser: feed correct sink (crucial)

This commit is contained in:
Robert Jördens 2016-10-13 15:17:38 +02:00
parent b1137563b3
commit 6a456bd7d4
1 changed files with 1 additions and 1 deletions
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artiq/gateware/targets/kc705.py
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@ -542,7 +542,7 @@ class Phaser(_NIST_Ions):
self.config["AD9154_DAC_CS"] = 1 << 0 self.config["AD9154_DAC_CS"] = 1 << 0
self.config["AD9154_CLK_CS"] = 1 << 1 self.config["AD9154_CLK_CS"] = 1 << 1
for i, ch in enumerate(sawgs): for i, ch in enumerate(sawgs):
conv = getattr(self.ad9154.jesd_core.transport.sink, conv = getattr(self.ad9154.jesd_core.sink,
"converter{}".format(i)) "converter{}".format(i))
# while at 5 GBps, take every second sample... FIXME # while at 5 GBps, take every second sample... FIXME
self.comb += conv.eq(Cat(ch.o[::2])) self.comb += conv.eq(Cat(ch.o[::2]))