From 6a456bd7d4d443c48a64867c546c7273a10a42a4 Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Thu, 13 Oct 2016 15:17:38 +0200 Subject: [PATCH] phaser: feed correct sink (crucial) --- artiq/gateware/targets/kc705.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/artiq/gateware/targets/kc705.py b/artiq/gateware/targets/kc705.py index 70ae7928a..8f6fc5c08 100755 --- a/artiq/gateware/targets/kc705.py +++ b/artiq/gateware/targets/kc705.py @@ -542,7 +542,7 @@ class Phaser(_NIST_Ions): self.config["AD9154_DAC_CS"] = 1 << 0 self.config["AD9154_CLK_CS"] = 1 << 1 for i, ch in enumerate(sawgs): - conv = getattr(self.ad9154.jesd_core.transport.sink, + conv = getattr(self.ad9154.jesd_core.sink, "converter{}".format(i)) # while at 5 GBps, take every second sample... FIXME self.comb += conv.eq(Cat(ch.o[::2]))