mirror of https://github.com/m-labs/artiq.git
coredevice: rename rtio to ttl, integrated in+out driver, loopback on the same pin in tests
This commit is contained in:
parent
62669f9ff2
commit
65b4b7bb12
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@ -1,7 +1,7 @@
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from artiq.language.core import *
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from artiq.language.db import *
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from artiq.language.units import *
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from artiq.coredevice import rtio
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from artiq.coredevice import ttl
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PHASE_MODE_DEFAULT = -1
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@ -14,7 +14,7 @@ class DDS(AutoDB):
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"""Core device Direct Digital Synthesis (DDS) driver.
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Controls DDS devices managed directly by the core device's runtime. It also
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uses a RTIO channel (through :class:`artiq.coredevice.rtio.RTIOOut`) to
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uses a RTIO TTL channel (through :class:`artiq.coredevice.ttl.TTLOut`) to
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control a RF switch that gates the output of the DDS device.
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:param dds_sysclk: DDS system frequency, used for computing the frequency
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@ -34,7 +34,7 @@ class DDS(AutoDB):
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self.previous_on = False
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self.previous_frequency = 0*MHz
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self.set_phase_mode(PHASE_MODE_CONTINUOUS)
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self.sw = rtio.RTIOOut(core=self.core, channel=self.rtio_switch)
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self.sw = ttl.TTLOut(core=self.core, channel=self.rtio_switch)
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@portable
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def frequency_to_ftw(self, frequency):
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@ -93,7 +93,7 @@ class DDS(AutoDB):
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self.set_phase_mode(phase_mode)
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if self.previous_frequency != frequency:
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merge = self.sw.previous_timestamp == time_to_cycles(now())
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merge = self.sw.o_previous_timestamp == time_to_cycles(now())
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if not merge:
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self.sw.sync()
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# Channel is already on:
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@ -14,7 +14,7 @@ llvm.initialize_all_asmprinters()
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_syscalls = {
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"watchdog_set": "i:i",
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"watchdog_clear": "i:n",
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"rtio_set_o": "Iii:n",
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"rtio_set_o": "Iib:n",
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"rtio_set_oe": "Iib:n",
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"rtio_set_sensitivity": "Iii:n",
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"rtio_get_counter": "n:I",
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@ -2,26 +2,21 @@ from artiq.language.core import *
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from artiq.language.db import *
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class LLRTIOOut(AutoDB):
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"""Low-level RTIO output driver.
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class LLTTLOut(AutoDB):
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"""Low-level RTIO TTL output driver.
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Allows setting RTIO outputs at arbitrary times, without time unit
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conversion.
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Allows setting RTIO TTL outputs at arbitrary times, without time
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unit conversion.
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This is meant to be used mostly in drivers; consider using
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``RTIOOut`` instead.
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``TTLOut`` instead.
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This should be used with output-only channels.
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"""
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class DBKeys:
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core = Device()
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channel = Argument()
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def build(self):
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self._set_oe()
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@kernel
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def _set_oe(self):
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syscall("rtio_set_oe", time_to_cycles(now()), self.channel, True)
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@kernel
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def set_o(self, t, value):
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"""Sets the output value of the RTIO channel.
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@ -37,7 +32,7 @@ class LLRTIOOut(AutoDB):
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:param t: timestamp in RTIO cycles (64-bit integer).
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"""
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self.set_o(t, 1)
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self.set_o(t, True)
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@kernel
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def off(self, t):
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@ -45,19 +40,13 @@ class LLRTIOOut(AutoDB):
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:param t: timestamp in RTIO cycles (64-bit integer).
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"""
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self.set_o(t, 0)
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self.set_o(t, False)
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class RTIOOut(AutoDB):
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"""RTIO output driver.
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class TTLOut(AutoDB):
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"""RTIO TTL output driver.
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Configures the corresponding RTIO channel as output on the core device and
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provides functions to set its level.
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This driver supports zero-length transition suppression. For example, if
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two pulses are emitted back-to-back with no delay between them, they will
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be merged into a single pulse with a duration equal to the sum of the
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durations of the original pulses.
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This should be used with output-only channels.
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:param core: core device
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:param channel: channel number
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@ -66,39 +55,31 @@ class RTIOOut(AutoDB):
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core = Device()
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channel = Argument()
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def build(self):
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self.previous_timestamp = int64(0) # in RTIO cycles
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self._set_oe()
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# in RTIO cycles
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self.o_previous_timestamp = int64(0)
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@kernel
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def _set_oe(self):
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syscall("rtio_set_oe", time_to_cycles(now()), self.channel, True)
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@kernel
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def _set_o(self, value):
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syscall("rtio_set_o", time_to_cycles(now()), self.channel, value)
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self.previous_timestamp = time_to_cycles(now())
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def _set_o(self, o):
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syscall("rtio_set_o", time_to_cycles(now()), self.channel, o)
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self.o_previous_timestamp = time_to_cycles(now())
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@kernel
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def sync(self):
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"""Busy-waits until all programmed level switches have been effected.
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This function is useful to synchronize CPU-controlled devices (such as
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the AD9858 DDS bus) with related RTIO controls (such as RF switches at
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the output of the DDS).
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"""
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while syscall("rtio_get_counter") < self.previous_timestamp:
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"""Busy-waits until all programmed level switches have been effected."""
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while syscall("rtio_get_counter") < self.o_previous_timestamp:
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pass
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@kernel
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def on(self):
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"""Sets the output to a logic high state."""
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self._set_o(1)
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self._set_o(True)
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@kernel
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def off(self):
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"""Sets the output to a logic low state."""
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self._set_o(0)
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self._set_o(False)
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@kernel
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def pulse(self, duration):
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@ -108,12 +89,20 @@ class RTIOOut(AutoDB):
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self.off()
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class RTIOIn(AutoDB):
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"""RTIO input driver.
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class TTLInOut(AutoDB):
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"""RTIO TTL input/output driver.
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Configures the corresponding RTIO channel as input on the core device and
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provides functions to analyze the incoming signal, with real-time gating
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to prevent overflows.
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In output mode, provides functions to set the logic level on the signal.
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In input mode, provides functions to analyze the incoming signal, with
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real-time gating to prevent overflows.
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RTIO TTLs supports zero-length transition suppression. For example, if
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two pulses are emitted back-to-back with no delay between them, they will
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be merged into a single pulse with a duration equal to the sum of the
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durations of the original pulses.
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This should be used with bidirectional channels.
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:param core: core device
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:param channel: channel number
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@ -123,17 +112,54 @@ class RTIOIn(AutoDB):
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channel = Argument()
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def build(self):
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self.previous_timestamp = int64(0) # in RTIO cycles
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self._set_oe()
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# in RTIO cycles
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self.o_previous_timestamp = int64(0)
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self.i_previous_timestamp = int64(0)
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@kernel
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def _set_oe(self):
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syscall("rtio_set_oe", time_to_cycles(now()), self.channel, False)
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def _set_oe(self, oe):
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syscall("rtio_set_oe", time_to_cycles(now()), self.channel, oe)
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@kernel
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def output(self):
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self._set_oe(True)
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@kernel
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def input(self):
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self._set_oe(False)
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@kernel
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def _set_o(self, o):
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syscall("rtio_set_o", time_to_cycles(now()), self.channel, o)
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self.o_previous_timestamp = time_to_cycles(now())
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@kernel
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def sync(self):
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"""Busy-waits until all programmed level switches have been effected."""
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while syscall("rtio_get_counter") < self.o_previous_timestamp:
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pass
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@kernel
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def on(self):
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"""Sets the output to a logic high state."""
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self._set_o(True)
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@kernel
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def off(self):
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"""Sets the output to a logic low state."""
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self._set_o(False)
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@kernel
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def pulse(self, duration):
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"""Pulses the output high for the specified duration."""
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self.on()
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delay(duration)
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self.off()
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@kernel
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def _set_sensitivity(self, value):
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syscall("rtio_set_sensitivity", time_to_cycles(now()), self.channel, value)
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self.previous_timestamp = time_to_cycles(now())
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self.i_previous_timestamp = time_to_cycles(now())
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@kernel
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def gate_rising(self, duration):
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@ -162,7 +188,8 @@ class RTIOIn(AutoDB):
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"""Poll the RTIO input during all the previously programmed gate
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openings, and returns the number of registered events."""
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count = 0
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while syscall("rtio_get", self.channel, self.previous_timestamp) >= 0:
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while syscall("rtio_get", self.channel,
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self.i_previous_timestamp) >= 0:
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count += 1
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return count
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@ -174,4 +201,4 @@ class RTIOIn(AutoDB):
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If the gate is permanently closed, returns a negative value.
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"""
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return cycles_to_time(syscall("rtio_get", self.channel,
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self.previous_timestamp))
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self.i_previous_timestamp))
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@ -1,7 +1,7 @@
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from artiq.language.core import *
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from artiq.language.db import *
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from artiq.language.units import *
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from artiq.coredevice import rtio
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from artiq.coredevice import ttl
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frame_setup = 20*ns
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@ -162,13 +162,13 @@ class CompoundPDQ2(AutoDB):
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def build(self):
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self.pdq2s = [self.dbh.get_device(d) for d in self.pdq2_devices]
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self.trigger = rtio.LLRTIOOut(
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self.trigger = ttl.LLTTLOut(
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core=self.core, channel=self.rtio_trigger)
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self.frame0 = rtio.LLRTIOOut(
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self.frame0 = ttl.LLTTLOut(
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core=self.core, channel=self.rtio_frame[0])
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self.frame1 = rtio.LLRTIOOut(
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self.frame1 = ttl.LLTTLOut(
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core=self.core, channel=self.rtio_frame[1])
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self.frame2 = rtio.LLRTIOOut(
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self.frame2 = ttl.LLTTLOut(
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core=self.core, channel=self.rtio_frame[2])
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self.frames = []
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@ -5,7 +5,7 @@ from fractions import Fraction
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from artiq import *
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from artiq.language.units import DimensionError
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from artiq.coredevice import comm_tcp, core, runtime_exceptions, rtio
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from artiq.coredevice import comm_tcp, core, runtime_exceptions, ttl
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from artiq.sim import devices as sim_devices
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@ -281,8 +281,7 @@ class ExecutionCase(unittest.TestCase):
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class _RTIOLoopback(AutoDB):
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class DBKeys:
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core = Device()
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i = Device()
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o = Device()
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io = Device()
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npulses = Argument()
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def report(self, n):
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@ -290,13 +289,15 @@ class _RTIOLoopback(AutoDB):
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@kernel
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def run(self):
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self.io.output()
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delay(1*us)
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with parallel:
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self.io.gate_rising(10*us)
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with sequential:
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for i in range(self.npulses):
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delay(25*ns)
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self.o.pulse(25*ns)
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self.i.gate_rising(10*us)
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self.report(self.i.count())
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self.io.pulse(25*ns)
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self.report(self.io.count())
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class _RTIOUnderflow(AutoDB):
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@ -335,8 +336,7 @@ class RTIOCase(unittest.TestCase):
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coredev = core.Core(comm=comm)
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uut = _RTIOLoopback(
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core=coredev,
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i=rtio.RTIOIn(core=coredev, channel=0),
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o=rtio.RTIOOut(core=coredev, channel=2),
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io=ttl.TTLInOut(core=coredev, channel=0),
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npulses=npulses
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)
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uut.run()
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@ -350,7 +350,7 @@ class RTIOCase(unittest.TestCase):
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coredev = core.Core(comm=comm)
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uut = _RTIOUnderflow(
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core=coredev,
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o=rtio.RTIOOut(core=coredev, channel=2)
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o=ttl.TTLOut(core=coredev, channel=2)
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)
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with self.assertRaises(runtime_exceptions.RTIOUnderflow):
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uut.run()
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@ -363,7 +363,7 @@ class RTIOCase(unittest.TestCase):
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coredev = core.Core(comm=comm)
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uut = _RTIOSequenceError(
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core=coredev,
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o=rtio.RTIOOut(core=coredev, channel=2)
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o=ttl.TTLOut(core=coredev, channel=2)
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)
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with self.assertRaises(runtime_exceptions.RTIOSequenceError):
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uut.run()
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@ -14,33 +14,15 @@
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"pmt0": {
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"type": "local",
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"module": "artiq.coredevice.rtio",
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"class": "RTIOIn",
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"module": "artiq.coredevice.ttl",
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"class": "TTLInOut",
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"arguments": {"channel": 0}
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},
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"pmt1": {
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"type": "local",
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"module": "artiq.coredevice.rtio",
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"class": "RTIOIn",
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"arguments": {"channel": 1}
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},
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"ttl0": {
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"type": "local",
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"module": "artiq.coredevice.rtio",
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"class": "RTIOOut",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 2}
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},
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"ttl1": {
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"type": "local",
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"module": "artiq.coredevice.rtio",
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"class": "RTIOOut",
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"arguments": {"channel": 3}
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},
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"ttl2": {
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"type": "local",
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"module": "artiq.coredevice.rtio",
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"class": "RTIOOut",
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"arguments": {"channel": 4}
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},
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}
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@ -11,17 +11,18 @@ class RTIOSkew(Experiment, AutoDB):
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class DBKeys:
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core = Device()
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pmt0 = Device()
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ttl0 = Device()
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rtio_skew = Result()
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@kernel
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def run(self):
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self.pmt0.output()
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delay(1*us)
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with parallel:
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self.pmt0.gate_rising(10*us)
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with sequential:
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delay(5*us)
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out_t = now()
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self.ttl0.pulse(5*us)
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self.pmt0.pulse(5*us)
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in_t = self.pmt0.timestamp()
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if in_t < 0*s:
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raise PulseNotReceived
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@ -3,10 +3,10 @@ Core drivers reference
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These drivers are for peripherals closely integrated into the core device, which do not use the controller mechanism.
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:mod:`artiq.coredevice.rtio` module
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:mod:`artiq.coredevice.ttl` module
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-----------------------------------
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.. automodule:: artiq.coredevice.rtio
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.. automodule:: artiq.coredevice.ttl
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:members:
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:mod:`artiq.coredevice.dds` module
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@ -14,39 +14,39 @@
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"pmt0": {
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"type": "local",
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"module": "artiq.coredevice.rtio",
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"class": "RTIOIn",
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"module": "artiq.coredevice.ttl",
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"class": "TTLInOut",
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"arguments": {"channel": 0}
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},
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"pmt1": {
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"type": "local",
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"module": "artiq.coredevice.rtio",
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"class": "RTIOIn",
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"module": "artiq.coredevice.ttl",
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"class": "TTLInOut",
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"arguments": {"channel": 1}
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},
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"ttl0": {
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"type": "local",
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"module": "artiq.coredevice.rtio",
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"class": "RTIOOut",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 2}
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},
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"ttl1": {
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"type": "local",
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"module": "artiq.coredevice.rtio",
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"class": "RTIOOut",
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"module": "artiq.coredevice.ttl",
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||||
"class": "TTLOut",
|
||||
"arguments": {"channel": 3}
|
||||
},
|
||||
"ttl2": {
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.rtio",
|
||||
"class": "RTIOOut",
|
||||
"module": "artiq.coredevice.ttl",
|
||||
"class": "TTLOut",
|
||||
"arguments": {"channel": 4}
|
||||
},
|
||||
"led": {
|
||||
"type": "local",
|
||||
"module": "artiq.coredevice.rtio",
|
||||
"class": "RTIOOut",
|
||||
"module": "artiq.coredevice.ttl",
|
||||
"class": "TTLOut",
|
||||
"arguments": {"channel": 18}
|
||||
},
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue