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artiq
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soc/target: remap RTIO to avoid conflict with Ethernet MAC+PHY

This commit is contained in:
Sebastien Bourdeauducq 2014-11-21 15:51:51 -08:00
parent 1f92e19f2b
commit 65567e1201
1 changed files with 1 additions and 1 deletions
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soc/targets/artiq.py
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@ -41,7 +41,7 @@ class _TestGen(Module):
class ARTIQMiniSoC(BaseSoC):
csr_map = {
"rtio": 12
"rtio": 13
}
csr_map.update(BaseSoC.csr_map)