diff --git a/soc/targets/artiq.py b/soc/targets/artiq.py
index aff07b227..a57a38111 100644
--- a/soc/targets/artiq.py
+++ b/soc/targets/artiq.py
@@ -41,7 +41,7 @@ class _TestGen(Module):
 
 class ARTIQMiniSoC(BaseSoC):
     csr_map = {
-        "rtio":            12
+        "rtio":            13
     }
     csr_map.update(BaseSoC.csr_map)