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test_dma: remove redundant clock

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mwojcik 2023-01-10 16:54:45 +08:00 committed by Sébastien Bourdeauducq
parent eb3742fb08
commit 627504b60e
1 changed files with 2 additions and 2 deletions
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4
artiq/gateware/test/rtio/test_dma.py
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@ -203,11 +203,11 @@ class TestDMA(unittest.TestCase):
run_simulation(tb[32], {"sys": [ run_simulation(tb[32], {"sys": [
do_dma(tb[32].dut, 0), monitor(32), do_dma(tb[32].dut, 0), monitor(32),
(None for _ in range(70)), (None for _ in range(70)),
]}, {"sys": 8, "sys": 8, "rio": 8, "rio_phy": 8}) ]}, {"sys": 8, "rio": 8, "rio_phy": 8})
run_simulation(tb[64], {"sys": [ run_simulation(tb[64], {"sys": [
do_dma(tb[64].dut, 0), monitor(64), do_dma(tb[64].dut, 0), monitor(64),
(None for _ in range(70)), (None for _ in range(70)),
]}, {"sys": 8, "sys": 8, "rio": 8, "rio_phy": 8}) ]}, {"sys": 8, "rio": 8, "rio_phy": 8})
correct_changes = [(timestamp + 11, channel) correct_changes = [(timestamp + 11, channel)
for channel, timestamp, _, _ in test_writes_full_stack] for channel, timestamp, _, _ in test_writes_full_stack]