mirror of https://github.com/m-labs/artiq.git
kasli: DRTIO support for Kasli 2
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parent
1f2182d4c7
commit
60e5f1c18e
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@ -306,7 +306,10 @@ class MasterBase(MiniSoC, AMPSoC):
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if enable_sata:
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drtio_data_pads.append(platform.request("sata"))
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drtio_data_pads += [platform.request("sfp", i) for i in range(1, 3)]
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if self.platform.hw_rev == "v2.0":
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drtio_data_pads.append(platform.request("sfp", 3))
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if self.platform.hw_rev in ("v1.0", "v1.1"):
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sfp_ctls = [platform.request("sfp_ctl", i) for i in range(1, 3)]
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self.comb += [sc.tx_disable.eq(0) for sc in sfp_ctls]
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@ -316,15 +319,19 @@ class MasterBase(MiniSoC, AMPSoC):
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sys_clk_freq=self.clk_freq,
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rtio_clk_freq=rtio_clk_freq)
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self.csr_devices.append("drtio_transceiver")
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self.sync += self.disable_si5324_ibuf.eq(
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self.sync += self.disable_cdr_clk_ibuf.eq(
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~self.drtio_transceiver.stable_clkin.storage)
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if enable_sata:
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sfp_channels = self.drtio_transceiver.channels[1:]
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else:
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sfp_channels = self.drtio_transceiver.channels
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if self.platform.hw_rev in ("v1.0", "v1.1"):
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self.comb += [sfp_ctl.led.eq(channel.rx_ready)
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for sfp_ctl, channel in zip(sfp_ctls, sfp_channels)]
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if self.platform.hw_rev == "v2.0":
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self.comb += [self.virtual_leds.get(i + 1).eq(channel.rx_ready)
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for i, channel in enumerate(sfp_channels)]
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self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
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@ -408,14 +415,17 @@ class MasterBase(MiniSoC, AMPSoC):
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def create_qpll(self):
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# The GTP acts up if you send any glitch to its
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# clock input, even while the PLL is held in reset.
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self.disable_si5324_ibuf = Signal(reset=1)
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self.disable_si5324_ibuf.attr.add("no_retiming")
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si5324_clkout = self.platform.request("si5324_clkout")
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si5324_clkout_buf = Signal()
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self.disable_cdr_clk_ibuf = Signal(reset=1)
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self.disable_cdr_clk_ibuf.attr.add("no_retiming")
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if self.platform.hw_rev == "v2.0":
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cdr_clk_clean = self.platform.request("cdr_clk_clean")
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else:
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cdr_clk_clean = self.platform.request("si5324_clkout")
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cdr_clk_clean_buf = Signal()
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self.specials += Instance("IBUFDS_GTE2",
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i_CEB=self.disable_si5324_ibuf,
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i_I=si5324_clkout.p, i_IB=si5324_clkout.n,
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o_O=si5324_clkout_buf)
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i_CEB=self.disable_cdr_clk_ibuf,
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i_I=cdr_clk_clean.p, i_IB=cdr_clk_clean.n,
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o_O=cdr_clk_clean_buf)
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# Note precisely the rules Xilinx made up:
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# refclksel=0b001 GTREFCLK0 selected
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# refclksel=0b010 GTREFCLK1 selected
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@ -430,7 +440,7 @@ class MasterBase(MiniSoC, AMPSoC):
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fbdiv=4,
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fbdiv_45=5,
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refclk_div=1)
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qpll = QPLL(si5324_clkout_buf, qpll_drtio_settings,
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qpll = QPLL(cdr_clk_clean_buf, qpll_drtio_settings,
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self.crg.clk125_buf, qpll_eth_settings)
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self.submodules += qpll
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self.drtio_qpll_channel, self.ethphy_qpll_channel = qpll.channels
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@ -452,27 +462,33 @@ class SatelliteBase(BaseSoC):
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platform = self.platform
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disable_si5324_ibuf = Signal(reset=1)
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disable_si5324_ibuf.attr.add("no_retiming")
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si5324_clkout = platform.request("si5324_clkout")
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si5324_clkout_buf = Signal()
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disable_cdr_clk_ibuf = Signal(reset=1)
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disable_cdr_clk_ibuf.attr.add("no_retiming")
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if self.platform.hw_rev == "v2.0":
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cdr_clk_clean = self.platform.request("cdr_clk_clean")
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else:
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cdr_clk_clean = self.platform.request("si5324_clkout")
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cdr_clk_clean_buf = Signal()
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self.specials += Instance("IBUFDS_GTE2",
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i_CEB=disable_si5324_ibuf,
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i_I=si5324_clkout.p, i_IB=si5324_clkout.n,
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o_O=si5324_clkout_buf)
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i_CEB=disable_cdr_clk_ibuf,
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i_I=cdr_clk_clean.p, i_IB=cdr_clk_clean.n,
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o_O=cdr_clk_clean_buf)
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qpll_drtio_settings = QPLLSettings(
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refclksel=0b001,
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fbdiv=4,
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fbdiv_45=5,
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refclk_div=1)
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qpll = QPLL(si5324_clkout_buf, qpll_drtio_settings)
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qpll = QPLL(cdr_clk_clean_buf, qpll_drtio_settings)
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self.submodules += qpll
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drtio_data_pads = []
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if enable_sata:
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drtio_data_pads.append(platform.request("sata"))
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drtio_data_pads += [platform.request("sfp", i) for i in range(3)]
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if self.platform.hw_rev == "v2.0":
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drtio_data_pads.append(platform.request("sfp", 3))
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if self.platform.hw_rev in ("v1.0", "v1.1"):
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sfp_ctls = [platform.request("sfp_ctl", i) for i in range(3)]
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self.comb += [sc.tx_disable.eq(0) for sc in sfp_ctls]
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self.submodules.drtio_transceiver = gtp_7series.GTP(
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@ -481,15 +497,19 @@ class SatelliteBase(BaseSoC):
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sys_clk_freq=self.clk_freq,
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rtio_clk_freq=rtio_clk_freq)
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self.csr_devices.append("drtio_transceiver")
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self.sync += disable_si5324_ibuf.eq(
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self.sync += disable_cdr_clk_ibuf.eq(
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~self.drtio_transceiver.stable_clkin.storage)
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if enable_sata:
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sfp_channels = self.drtio_transceiver.channels[1:]
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else:
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sfp_channels = self.drtio_transceiver.channels
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if self.platform.hw_rev in ("v1.0", "v1.1"):
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self.comb += [sfp_ctl.led.eq(channel.rx_ready)
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for sfp_ctl, channel in zip(sfp_ctls, sfp_channels)]
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if self.platform.hw_rev == "v2.0":
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self.comb += [self.virtual_leds.get(i).eq(channel.rx_ready)
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for i, channel in enumerate(sfp_channels)]
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self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3)
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@ -538,7 +558,8 @@ class SatelliteBase(BaseSoC):
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self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
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self.submodules.siphaser = SiPhaser7Series(
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si5324_clkin=platform.request("si5324_clkin"),
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si5324_clkin=platform.request("cdr_clk") if platform.hw_rev == "v2.0"
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else platform.request("si5324_clkin"),
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rx_synchronizer=self.rx_synchronizer,
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ref_clk=self.crg.clk125_div2, ref_div2=True,
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rtio_clk_freq=rtio_clk_freq)
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