From 5f083f21a4c1eb58726fe0ba2fbbb431645d743e Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Sun, 8 Oct 2017 22:37:46 +0800
Subject: [PATCH] rtio/dma: fix signal width

---
 artiq/gateware/rtio/dma.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/artiq/gateware/rtio/dma.py b/artiq/gateware/rtio/dma.py
index 0ea364ef8..a8b7c9195 100644
--- a/artiq/gateware/rtio/dma.py
+++ b/artiq/gateware/rtio/dma.py
@@ -254,7 +254,7 @@ class CRIMaster(Module, AutoCSR):
 
         # # #
 
-        underflow_trigger = Signal(2)
+        underflow_trigger = Signal()
         self.sync += [
             If(underflow_trigger,
                 self.underflow.w.eq(1),