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cri: fix routing table depth

This commit is contained in:
Sebastien Bourdeauducq 2018-09-12 17:30:55 +08:00
parent edf403b837
commit 5bcd40ff59
1 changed files with 1 additions and 1 deletions
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artiq/gateware/rtio/cri.py
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@ -130,7 +130,7 @@ class CRIDecoder(Module, AutoCSR):
selected = Signal(slave_bits) selected = Signal(slave_bits)
if enable_routing: if enable_routing:
self.specials.routing_table = Memory(slave_bits, 8) self.specials.routing_table = Memory(slave_bits, 256)
rtp_csr = self.routing_table.get_port(write_capable=True) rtp_csr = self.routing_table.get_port(write_capable=True)
self.specials += rtp_csr self.specials += rtp_csr