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test_rtio: port imports to NAC3

This commit is contained in:
Sebastien Bourdeauducq 2022-02-26 18:52:56 +08:00
parent a606afa3bd
commit 5acf008be3
1 changed files with 2 additions and 3 deletions
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5
artiq/test/coredevice/test_rtio.py
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@ -12,7 +12,6 @@ from artiq.coredevice import exceptions
from artiq.coredevice.comm_mgmt import CommMgmt from artiq.coredevice.comm_mgmt import CommMgmt
from artiq.coredevice.comm_analyzer import (StoppedMessage, OutputMessage, InputMessage, from artiq.coredevice.comm_analyzer import (StoppedMessage, OutputMessage, InputMessage,
decode_dump, get_analyzer_dump) decode_dump, get_analyzer_dump)
from artiq.compiler.targets import CortexA9Target
artiq_low_latency = os.getenv("ARTIQ_LOW_LATENCY") artiq_low_latency = os.getenv("ARTIQ_LOW_LATENCY")
@ -466,7 +465,7 @@ class CoredeviceTest(ExperimentCase):
rate = self.dataset_mgr.get("pulse_rate") rate = self.dataset_mgr.get("pulse_rate")
print(rate) print(rate)
self.assertGreater(rate, 100*ns) self.assertGreater(rate, 100*ns)
if exp.core.target_cls == CortexA9Target: if exp.core.target == "cortexa9":
# Crappy AXI PS/PL interface from Xilinx is slow. # Crappy AXI PS/PL interface from Xilinx is slow.
self.assertLess(rate, 810*ns) self.assertLess(rate, 810*ns)
else: else:
@ -728,7 +727,7 @@ class DMATest(ExperimentCase):
raise unittest.SkipTest("skipped on Kasli for now") raise unittest.SkipTest("skipped on Kasli for now")
exp = self.create(_DMA) exp = self.create(_DMA)
is_zynq = exp.core.target_cls == CortexA9Target is_zynq = exp.core.target == "cortexa9"
count = 20000 count = 20000
exp.record_many(40) exp.record_many(40)
exp.playback_many(count, is_zynq) exp.playback_many(count, is_zynq)