From 5acf008be376ee4820f744097da526e7626b9397 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sat, 26 Feb 2022 18:52:56 +0800 Subject: [PATCH] test_rtio: port imports to NAC3 --- artiq/test/coredevice/test_rtio.py | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/artiq/test/coredevice/test_rtio.py b/artiq/test/coredevice/test_rtio.py index 3313b5c14..20a8d0ed6 100644 --- a/artiq/test/coredevice/test_rtio.py +++ b/artiq/test/coredevice/test_rtio.py @@ -12,7 +12,6 @@ from artiq.coredevice import exceptions from artiq.coredevice.comm_mgmt import CommMgmt from artiq.coredevice.comm_analyzer import (StoppedMessage, OutputMessage, InputMessage, decode_dump, get_analyzer_dump) -from artiq.compiler.targets import CortexA9Target artiq_low_latency = os.getenv("ARTIQ_LOW_LATENCY") @@ -466,7 +465,7 @@ class CoredeviceTest(ExperimentCase): rate = self.dataset_mgr.get("pulse_rate") print(rate) self.assertGreater(rate, 100*ns) - if exp.core.target_cls == CortexA9Target: + if exp.core.target == "cortexa9": # Crappy AXI PS/PL interface from Xilinx is slow. self.assertLess(rate, 810*ns) else: @@ -728,7 +727,7 @@ class DMATest(ExperimentCase): raise unittest.SkipTest("skipped on Kasli for now") exp = self.create(_DMA) - is_zynq = exp.core.target_cls == CortexA9Target + is_zynq = exp.core.target == "cortexa9" count = 20000 exp.record_many(40) exp.playback_many(count, is_zynq)