mirror of https://github.com/m-labs/artiq.git
sayma_amc: refactor RTM FPGA code
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@ -77,11 +77,8 @@ class AD9154NoSAWG(Module, AutoCSR):
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Cat(samples[3]).eq(Cat(samples[1]))
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]
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class RTMCommon:
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def __init__(self):
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platform = self.platform
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class RTMUARTForward(Module):
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def __init__(self, platform):
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# forward RTM UART to second FTDI UART channel
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serial_1 = platform.request("serial", 1)
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serial_rtm = platform.request("serial_rtm")
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@ -90,6 +87,11 @@ class RTMCommon:
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serial_rtm.tx.eq(serial_1.rx)
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]
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class RTMSerWb:
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def __init__(self):
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platform = self.platform
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# RTM bitstream upload
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slave_fpga_cfg = self.platform.request("rtm_fpga_cfg")
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self.submodules.slave_fpga_cfg = gpio.GPIOTristate([
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@ -153,13 +155,7 @@ class Master(MiniSoC, AMPSoC):
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platform = self.platform
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rtio_clk_freq = 150e6
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# forward RTM UART to second FTDI UART channel
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serial_1 = platform.request("serial", 1)
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serial_rtm = platform.request("serial_rtm")
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self.comb += [
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serial_1.tx.eq(serial_rtm.rx),
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serial_rtm.tx.eq(serial_1.rx)
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]
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self.submodules += RTMUARTForward(platform)
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self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
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self.csr_devices.append("si5324_rst_n")
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@ -283,7 +279,7 @@ class Master(MiniSoC, AMPSoC):
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self.csr_devices.append("routing_table")
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class Satellite(BaseSoC, RTMCommon):
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class Satellite(BaseSoC, RTMSerWb):
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"""
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DRTIO satellite with local DAC/SAWG channels.
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Use SFP0 to connect to master (Kasli/Sayma).
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@ -300,13 +296,15 @@ class Satellite(BaseSoC, RTMCommon):
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sdram_controller_type="minicon",
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l2_size=128*1024,
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**kwargs)
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RTMCommon.__init__(self)
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RTMSerWb.__init__(self)
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add_identifier(self, suffix=".without-sawg" if not with_sawg else "")
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self.config["HMC830_REF"] = "150"
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platform = self.platform
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rtio_clk_freq = 150e6
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self.submodules += RTMUARTForward(platform)
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rtio_channels = []
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for i in range(4):
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phy = ttl_simple.Output(platform.request("user_led", i))
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