mirror of https://github.com/m-labs/artiq.git
rtio: remove unnecessary attributes
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cd587e4f12
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57d633f48e
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@ -26,6 +26,7 @@ class DDS(AutoContext):
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parameters = "dds_sysclk reg_channel rtio_switch"
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def build(self):
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self.previous_on = False
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self.previous_frequency = 0*MHz
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self.set_phase_mode(PHASE_MODE_CONTINUOUS)
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self.sw = rtio.RTIOOut(self, channel=self.rtio_switch)
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@ -95,7 +96,7 @@ class DDS(AutoContext):
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# Channel is off:
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# Use soft timing on FUD to prevent conflicts when reprogramming
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# several channels that need to be turned on at the same time.
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rt_fud = merge or bool(self.sw.previous_value)
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rt_fud = merge or self.previous_on
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ftw = self.frequency_to_ftw(frequency)
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if self.phase_mode != PHASE_MODE_CONTINUOUS:
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phase_per_microcycle = ftw*int64(
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@ -108,6 +109,7 @@ class DDS(AutoContext):
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rt_fud, self.phase_mode == PHASE_MODE_TRACKING)
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self.previous_frequency = frequency
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self.sw.on()
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self.previous_on = True
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if phase_mode != PHASE_MODE_DEFAULT:
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self.set_phase_mode(old_phase_mode)
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@ -118,6 +120,7 @@ class DDS(AutoContext):
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"""
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self.sw.off()
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self.previous_on = False
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@kernel
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def pulse(self, frequency, duration,
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@ -14,7 +14,6 @@ class LLRTIOOut(AutoContext):
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parameters = "channel"
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def build(self):
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self.previous_timestamp = int64(0) # in RTIO cycles
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self._set_oe()
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@kernel
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@ -30,7 +29,6 @@ class LLRTIOOut(AutoContext):
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"""
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syscall("rtio_set", t, self.channel, value)
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self.previous_timestamp = t
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@kernel
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def on(self, t):
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@ -56,7 +54,6 @@ class _RTIOBase(AutoContext):
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def build(self):
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self.previous_timestamp = int64(0) # in RTIO cycles
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self.previous_value = 0
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@kernel
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def _set_oe(self, oe):
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@ -66,7 +63,6 @@ class _RTIOBase(AutoContext):
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def _set_value(self, value):
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syscall("rtio_set", time_to_cycles(now()), self.channel, value)
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self.previous_timestamp = time_to_cycles(now())
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self.previous_value = value
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class RTIOOut(_RTIOBase):
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